ADV7170/ADV7171
V
AA
= 3.0 V to 3.6 V
, V
REF
= 1.235 V, R
SET
= 150 Ω. All specifications T
MIN
to T
MAX 2
Table 6.
Parameter
MPU PORT
SCLOCK Frequency
SCLOCK High Pulse Width, t
1
SCLOCK Low Pulse Width, t
2
Hold Time (Start Condition), t
3
Setup Time (Start Condition), t
4
Data Setup Time, t
5
SDATA, SCLOCK Rise Time, t
6
SDATA, SCLOCK Fall Time, t
7
Setup Time (Stop Condition), t
8
ANALOG OUTPUTS
Analog Output Delay
DAC Analog Output Skew
CLOCK CONTROL AND PIXEL PORT
f
CLOCK
Clock High Time, t
9
Clock Low Time, t
10
Data Setup Time, t
11
Data Hold Time, t
12
Control Setup Time, t
11
Control Hold Time, t
12
Digital Output Access Time, t
13
Digital Output Hold Time, t
14
Pipeline Delay, t
15
TELETEXT
Digital Output Access Time, t
16
Data Setup Time, t
17
Data Hold Time, t
18
RESET CONTROL
RESET Low Time
1
2
Conditions
Min
0
0.6
1.3
0.6
0.6
100
Typ
Max
400
Unit
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
ns
ns
ns
After this period the first clock is generated
Relevant for repeated start condition
300
300
0.6
7
0
27
8
8
3.5
4
4
3
12
8
48
23
2
6
6
The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range.
Ambient temperature range T
MIN
to T
MAX
: −40°C to +85°C. The die temperature, T
J
, must always be kept below 110°C.
3
TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load ≤10 pF.
4
Guaranteed by characterization
5
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition
6
Pixel Port consists of the following:
Pixel inputs:
P15–P0
Pixel controls: HSYNC, FIELD/VSYNC, BLANK
Clock input:
CLOCK
7
Teletext port consists of the following:
Teletext output: TTXREQ
Teletext input: TTX
Rev. C | Page 8 of 64
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