ADV7125
3.3 V TIMING SPECIFICATIONS
V
AA
= 3.0 V to 3.6 V,
V
REF
= 1.235 V, R
SET
= 560 Ω, C
L
= 10 pF. All specifications T
MIN
to T
MAX
,
2
unless otherwise noted, T
J MAX
= 110°C.
Table 4.
Parameter
ANALOG OUTPUTS
Analog Output Delay,
Analog Output Rise/Fall Time
Analog Output Transition Time
Analog Output Skew
6
CLOCK CONTROL
CLOCK Frequency
7
Symbol
t
6
t
7
t
8
t
9
f
CLK
Min
Typ
7.5
1.0
15
1
Max
Unit
ns
ns
ns
ns
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
50 MHz grade
140 MHz grade
240 MHz grade
330 MHz grade
Conditions
2
50
140
240
330
CLOCK Period
CLOCK Pulse Width High
CLOCK Pulse Width Low
PSAVE Up Time
1
2
t
1
t
2
t
3
t
4
t
5
t
4
t
5
t
4
t
5
t
4
t
5
t
PD
t
10
0.2
1.5
3
1.4
1.4
1.875
1.875
2.85
2.85
8.0
8.0
1.0
f
CLK_MAX
= 330 MHz
f
CLK_MAX
= 330 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 240 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 140 MHz
f
CLK_MAX
= 50 MHz
f
CLK_MAX
= 50 MHz
1.0
4
1.0
10
These maximum and minimum specifications are guaranteed over this range.
Temperature range: T
MIN
to T
MAX
: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz.
3
Timing specifications are measured with input levels of 3.0 V (V
IH
) and 0 V (V
IL
) for 3.3 V supplies.
4
Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5
Measured from 50% point of full-scale transition to 2% of final value.
6
Guaranteed by characterization.
7
f
CLK
maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
t
3
t
4
t
5
CLOCK
t
2
DIGITAL INPUTS
(R7 TO R0, G7 TO G0, B7 TO B0,
SYNC, BLANK)
t
1
t
6
t
8
ANALOG OUTPUTS
(IOR, IOR, IOG, IOG, IOB, IOB)
t
7
NOTES
1. OUTPUT DELAY (
t
6
) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
OF FULL-SCALE TRANSITION.
2. OUTPUT RISE/FALL TIME (
t
7
) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (
t
8
) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
FINAL OUTPUT VALUE.
Figure 2. Timing Diagram
Rev. C | Page 6 of 16
03097-002