欢迎访问ic37.com |
会员登录 免费注册
发布采购

ADV7125JSTZ240 参数 Datasheet PDF下载

ADV7125JSTZ240图片预览
型号: ADV7125JSTZ240
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , 330 MHz三通道,8位高速视频DAC [CMOS, 330 MHz Triple 8-Bit High Speed Video DAC]
分类和应用: 转换器数模转换器PC
文件页数/大小: 16 页 / 293 K
品牌: AD [ ANALOG DEVICES ]
 浏览型号ADV7125JSTZ240的Datasheet PDF文件第5页浏览型号ADV7125JSTZ240的Datasheet PDF文件第6页浏览型号ADV7125JSTZ240的Datasheet PDF文件第7页浏览型号ADV7125JSTZ240的Datasheet PDF文件第8页浏览型号ADV7125JSTZ240的Datasheet PDF文件第10页浏览型号ADV7125JSTZ240的Datasheet PDF文件第11页浏览型号ADV7125JSTZ240的Datasheet PDF文件第12页浏览型号ADV7125JSTZ240的Datasheet PDF文件第13页  
ADV7125
Pin Number
37
Mnemonic
R
SET
Description
A resistor (R
SET
) connected between this pin and GND controls the magnitude of the full-scale video
signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The
relationship between R
SET
and the full-scale output current on IOG (assuming I
SYNC
is connected to IOG)
is given by:
R
SET
(Ω) = 11,445 ×
V
REF
(V)/IOG (mA)
The relationship between R
SET
and the full-scale output current on IOR, IOG, and IOB is given by:
IOG
(mA) = 11,444.8 ×
V
REF
(V)/R
SET
(Ω) (SYNC being asserted)
IOR, IOB
(mA) = 7989.6 ×
V
REF
(V)/R
SET
(Ω)
The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC
tied permanently low.
Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is
active.
The LFCSP_VQ has an exposed paddle that must be connected to GND.
38
49 (EPAD)
PSAVE
EP (EPAD)
Rev. C | Page 9 of 16