ADV7125
Z
Z
1
2
Figure 5 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 ꢁ load of
Figure 6. As well as the gray scale levels (black level to white
+V
4
0.1µF
S
2
3
Z
= 75Ω
0
75Ω
IOR, IOG, IOB
DACs
SYNC
level), Figure 5 also shows the contributions of
and
AD848
7
BLANK
for the ADV7125. These control inputs add appro-
(CABLE)
Z
= 75Ω
0.1µF
6
L
(MONITOR)
priately weighted currents to the analog outputs, producing
the specific output level requirements for video applications.
Z
= 75Ω
S
–V
S
(SOURCE
TERMINATION)
Z
1
GAIN (G) = 1 +
SYNC
BLANK
Table 7 details how the
output levels.
and
inputs modify the
Z
2
Figure 9. AD848 As an Output Buffer
GRAY SCALE OPERATION
PCB LAYOUT CONSIDERATIONS
The ADV7125 can be used for standalone, gray scale (mono-
chrome) or composite video applications (that is, only one channel
used for video information). Any one of the three channels, red,
green, or blue, can be used to input the digital video data. The
two unused video data channels should be tied to Logic 0. The
unused analog outputs should be terminated with the same load
as that for the used channel, that is, if the red channel is used
and IOR is terminated with a doubly terminated 75 ꢁ load
(37.5 ꢁ), IOB and IOG should be terminated with 37.5 ꢁ
resistors (see Figure 8).
The ADV7125 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7125, it is imperative
that great care be given to the PCB layout. Figure 10 shows a
recommended connection diagram for the ADV7125.
The layout should be optimized for lowest noise on the
ADV7125 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling.
Shorten the lead length between groups of VAA and GND pins
to minimize inductive ringing.
DOUBLY
R0
R7
IOR
IOG
TERMINATED
VIDEO
OUTPUT
It is recommended to use a 4-layer printed circuit board with a
single ground plane. The ground and power planes should
separate the signal trace layer and the solder side layer. Noise
on the analog power plane can be further reduced by using
multiple decoupling capacitors (see Figure 10). Optimum
performance is achieved by using 0.1 μF and 0.01 μF ceramic
capacitors. Individually decouple each VAA pin to ground by
placing the capacitors as close as possible to the device with the
capacitor leads as short as possible, thus minimizing lead
inductance. It is important to note that while the ADV7125
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) provides EMI
suppression between the switching power supply and the main
PCB. Alternatively, consideration can be given to using a 3-
terminal voltage regulator.
75Ω LOAD
37.5Ω
37.5Ω
ADV7125
G0
G7
IOB
B0
B7
GND
Figure 8. Input and Output Connections for Standalone Gray Scale or
Composite Video
VIDEO OUTPUT BUFFERS
The ADV7125 is specified to drive transmission line loads. The
analog output configuration to drive such loads is described in the
Analog Outputs section and illustrated in Figure 9. However,
in some applications, it may be required to drive long transmis-
sion line cable lengths. Cable lengths greater than 10 meters can
attenuate and distort high frequency analog output pulses. The
inclusion of output buffers compensates for some cable distortion.
Buffers with large full power bandwidths and gains between
two and four are required. These buffers also need to be able
to supply sufficient current over the complete output voltage
swing. Analog Devices produces a range of suitable op amps for
such applications. These include the AD843, AD844, AD847,
and AD848 series of monolithic op amps. In very high frequency
applications (80 MHz), the AD8061 is recommended. More
information on line driver buffering circuits is given in the
relevant op amp data sheets.
DIGITAL SIGNAL INTERCONNECT
Isolate the digital signal lines to the ADV7125 as much as
possible from the analog outputs and other analog circuitry.
Digital signal lines should not overlay the analog power plane.
Due to the high clock rates used, long clock lines to the
ADV7125 should be avoided to minimize noise pickup.
Connect any active pull-up termination resistors for the digital
inputs to the regular PCB power plane (VCC) and not to the
analog power plane.
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit results in any desired video level.
Rev. C | Page 13 of 16
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