ADV7125
5 V TIMING SPECIFICATIONS
VAA = 5 V 5ꢀ,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 3.
Parameter3
Symbol Min
Typ
Max
Unit
Conditions
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Timeꢀ
Analog Output Transition Timeꢁ
Analog Output Skew6
CLOCK CONTROL
t6
t7
t8
t9
ꢁ.ꢁ
1.±
1ꢁ
1
ns
ns
ns
ns
2
CLOCK Frequency7
fCLK
±.ꢁ
ꢁ±
MHz
ꢁ± MHz grade
1ꢀ± MHz grade
2ꢀ± MHz grade
±.ꢁ
±.ꢁ
±.ꢁ
1.ꢁ
ꢀ.17
1.87ꢁ
1.87ꢁ
2.8ꢁ
2.8ꢁ
8.±
1ꢀ±
2ꢀ±
MHz
MHz
ns
ns
ns
ns
ns
ns
Data and Control Setup6
Data and Control Hold6
CLOCK Period
t1
t2
t3
tꢀ
tꢁ
tꢀ
tꢁ
tꢀ
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High6
CLOCK Pulse Width Low6
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay6
fCLK_MAX = 2ꢀ± MHz
fCLK_MAX = 2ꢀ± MHz
fCLK_MAX = 1ꢀ± MHz
fCLK_MAX = 1ꢀ± MHz
fCLK_MAX = ꢁ± MHz
fCLK_MAX = ꢁ± MHz
ns
ns
ns
tꢁ
tPD
t1±
8.±
1.±
1.±
2
1.±
1±
Clock cycles
ns
PSAVE Up Time6
1 The maximum and minimum specifications are guaranteed over this range.
2 Temperature range TMIN to TMAX: −ꢀ±°C to +8ꢁ°C at ꢁ± MHz and 1ꢀ± MHz, ±°C to +7±°C at 2ꢀ± MHz.
3 Timing specifications are measured with input levels of 3.± V (VIH) and ± V (VIL) for both ꢁ V and 3.3 V supplies.
ꢀ Rise time was measured from the 1±% to 9±% point of zero to full-scale transition, fall time from the 9±% to 1±% point of a full-scale transition.
ꢁ Measured from ꢁ±% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 12ꢁ MHz and ꢁ V. Limits specified here are guaranteed by characterization.
Rev. C | Page ꢁ of 16
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