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ADV7125BCPZ170-RL 参数 Datasheet PDF下载

ADV7125BCPZ170-RL图片预览
型号: ADV7125BCPZ170-RL
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS , 330 MHz三通道,8位高速视频DAC [CMOS, 330 MHz Triple 8-Bit High Speed Video DAC]
分类和应用: 转换器数模转换器
文件页数/大小: 16 页 / 293 K
品牌: ADI [ ADI ]
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ADV7125  
SPECIFICATIONS  
5 V ELECTRICAL CHARACTERISTICS  
VAA = 5 V 5ꢀ, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.  
Table 1.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions1  
Guaranteed Monotonic  
VIN = ±.± V or VDD  
STATIC PERFORMANCE  
Resolution (Each DAC)  
Integral Nonlinearity (BSL)  
Differential Nonlinearity  
DIGITAL AND CONTROL INPUTS  
Input High Voltage, VIH  
Input Low Voltage, VIL  
Input Current, IIN  
8
−1  
−1  
Bits  
LSB  
LSB  
±±.ꢀ  
±±.2ꢁ  
+1  
+1  
2
V
V
μA  
μA  
pF  
±.8  
+1  
−1  
PSAVE Pull-Up Current  
2±  
1±  
Input Capacitance, CIN  
ANALOG OUTPUTS  
Output Current  
Green DAC, SYNC = high  
RGB DAC, SYNC = low  
2.±  
2.±  
26.ꢁ  
18.ꢁ  
mA  
mA  
%
V
kΩ  
pF  
% FSR  
% FSR  
DAC-to-DAC Matching  
Output Compliance Range, VOC  
Output Impedance, ROUT  
Output Capacitance, COUT  
Offset Error  
1.±  
±
1.ꢀ  
1±±  
1±  
IOUT = ± mA  
Tested with DAC output = ± V  
FSR = 18.62 mA  
−±.±2ꢁ  
−ꢁ.±  
+±.±2ꢁ  
+ꢁ.±  
Gain Error2  
VOLTAGE REFERENCE, EXTERNAL AND  
INTERNAL  
Reference Range, VREF  
POWER DISSIPATION  
Digital Supply Current3  
1.12  
1.23ꢁ  
1.3ꢁ  
V
3.ꢀ  
1±.ꢁ  
18  
67  
8
9
mA  
mA  
mA  
mA  
mA  
mA  
%/%  
fCLK = ꢁ± MHz  
fCLK = 1ꢀ± MHz  
fCLK = 2ꢀ± MHz  
RSET = ꢁ3± Ω  
RSET = ꢀ933 Ω  
PSAVE = low, digital, and control inputs at VDD  
1ꢁ  
2ꢁ  
72  
Analog Supply Current  
Standby Supply Currentꢀ  
2.1  
±.1  
ꢁ.±  
±.ꢁ  
Power Supply Rejection Ratio  
1 Temperature range TMIN to TMAX: −ꢀ±°C to +8ꢁ°C at ꢁ± MHz and 1ꢀ± MHz, ±°C to +7±°C at 2ꢀ± MHz and 33± MHz.  
2 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 1±±), where Ideal = VREF/RSET × K × (±xFFH) × ꢀ and K = 7.9896.  
3 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at ± V and VDD  
These maximum/minimum specifications are guaranteed by characterization in the ꢀ.7ꢁ V to ꢁ.2ꢁ V range.  
.
Rev. C | Page 3 of 16  
 
 
 
 
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