ADuM1400/ADuM1401/ADuM1402
Parameter
Pulse Width Distortion, |t
PLH
− t
PHL
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching
ADuM140xBRW
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching, Codirectional
Channels
Channel-to-Channel Matching, Opposing-
Directional Channels
ADuM140xCRW
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |t
PLH
− t
PHL
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching, Codirectional
Channels
Channel-to-Channel Matching, Opposing-
Directional Channels
For All Models
Output Disable Propagation Delay (High/Low
to High Impedance)
Output Enable Propagation Delay (High
Impedance to High/Low
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at Logic
High Output
Common-Mode Transient Immunity at Logic
Low Output
Refresh Rate
Input Dynamic Supply Current per Channel
Output Dynamic Supply Current per Channel
1
2
Symbol
PWD
t
PSK
t
PSKCD
/t
PSKOD
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
Min
Typ
11
Max Unit
40
ns
ps/°C
50
ns
50
ns
100
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
Test Conditions
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
10
20
32
5
50
3
15
3
6
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
90
18
8.3
120
27
0.5
3
11.1 ns
Mbps
32
ns
2
ns
ps/°C
10
ns
2
ns
5
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
t
PHZ
, t
PLH
t
PZH
, t
PZL
t
R
/t
F
|CM
H
|
|CM
L
|
f
r
I
DDI (D)
I
DDO (D)
6
6
2.5
35
35
1.2
0.19
0.05
8
8
ns
ns
ns
kV/μs
kV/μs
Mbps
mA/Mbps
mA/Mbps
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1
or V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
25
25
All voltages are relative to their respective ground.
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section.
See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through
DD1
and V
DD2
supply currents as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
6
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Rev. G | Page 5 of 32
AD [ ANALOG DEVICES ]
