ADuM1300/ADuM1301
Parameter
90 Mbps (CRW Grade Only)
V
DD1
Supply Current
5 V/3 V Operation
3 V/5 V Operation
V
DD2
Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
Logic High Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic Low Input Threshold
5 V/3 V Operation
3 V/5 V Operation
Logic High Output Voltages
Symbol
I
DD1 (90)
43
24
I
DD2 (90)
16
29
I
IA
, I
IB
, I
IC
,
I
E1
, I
E2
V
IH
, V
EH
–10
+0.01
23
37
+10
mA
mA
µA
45 MHz logic signal freq.
45 MHz logic signal freq.
0 ≤ V
IA
,V
IB
, V
IC
≤ V
DD1
or V
DD2
,
0 ≤ V
E1
,V
E2
≤ V
DD1
or V
DD2
57
36
mA
mA
45 MHz logic signal freq.
45 MHz logic signal freq.
Min
Typ
Max Unit
Test Conditions
2.0
1.6
V
IL
, V
EL
0.8
0.4
V
OAH
, V
OBH
,
V
OCH
V
DD1
, V
DD2
–
0.1
V
DD1
,
V
DD2
– 0.4
V
DD1
/V
DD2
V
DD1
/
V
DD2
– 0.2
0.0
0.1
0.04
0.1
0.2
0.4
V
V
V
V
V
V
V
V
V
I
Ox
= –20 µA, V
Ix
= V
IxH
I
Ox
= –4 mA, V
Ix
= V
IxH
I
Ox
= 20 µA, V
Ix
= V
IxL
I
Ox
= 400 µA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
Logic Low Output Voltages
V
OAL
, V
OBL
, V
OCL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
PLH
– t
PHL
Propagation Delay Skew
Channel-to-Channel Matching
ADuM130xBRW
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
PLH
– t
PHL
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
ADuM130xCRW
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse-Width Distortion, |t
PLH
-t
PHL
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
Opposing-Directional Channels
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
10
15
35
5
1
50
70
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
100
50
3
6
3
22
ns
Mbps
ns
ns
ps/°C
ns
ns
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF,CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD
t
PSKOD
90
20
8.3
120
30
0.5
3
11.1 ns
Mbps
40
ns
2
ns
ps/°C
14
ns
2
ns
5
ns
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
Rev. C | Page 8 of 20
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