Timer Clock Timing
and
describe timer clock timing.
Table 35. Timer Clock Timing
Parameter
Switching Characteristic
t
TODP
Timer Output Update Delay After PPI_CLK High
Min
Max
12
Unit
ns
PPI_CLK
t
TODP
TMRx OUTPUT
Figure 30. Timer Clock Timing
Timer Cycle Timing
and
describe timer expired operations. The
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of f
SCLK
/2 MHz.
Table 36. Timer Cycle Timing
V
DDEXT
= 1.8 V
Min
Max
1 × t
SCLK
1 × t
SCLK
8.0
1.5
1 × t
SCLK
(2
32
–1) × t
SCLK
7.5
V
DDEXT
= 2.5 V/3.3 V
Min
Max
1 × t
SCLK
1 × t
SCLK
6.5
1.5
1 × t
SCLK
(2
32
–1) × t
SCLK
6.5
Parameter
Timing Characteristics
t
WL
Timer Pulse Width Low
1
t
WH
Timer Pulse Width High
t
TIS
Timer Input Setup Time Before CLKOUT Low
2
t
TIH
Timer Input Hold Time After CLKOUT Low
Switching Characteristics
t
HTO
Timer Pulse Width Output
t
TOD
Timer Output Update Delay After CLKOUT High
1
2
Unit
ns
ns
ns
ns
ns
ns
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
CLKOUT
t
TOD
TMRx OUTPUT
t
TIS
TMRx INPUT
t
TIH
t
HTO
t
WH
,t
WL
Figure 31. Timer PWM_OUT Cycle Timing
Rev. I
|
Page 41 of 64 |
August 2013
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