General-Purpose I/O Port F Pin Cycle Timing
Table 34. General-Purpose I/O Port F Pin Cycle Timing
V
DDEXT
= 1.8 V
Min
Max
t
SCLK
+ 1
6
V
DDEXT
= 2.5 V/3.3 V
Min
Max
Unit
t
SCLK
+ 1
6
ns
ns
Parameter
Timing Requirement
t
WFI
GPIO Input Pulse Width
Switching Characteristic
t
GPOD
GPIO Output Delay from CLKOUT Low
CLKOUT
t
GPOD
GPIO OUTPUT
t
WFI
GPIO INPUT
Figure 29. GPIO Cycle Timing
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
For information on the UART port receive and transmit opera-
tions, see the
ADSP-BF533 Blackfin Processor Hardware
Reference.
Rev. I
|
Page 40 of 64 |
August 2013
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