ADSP-BF531/ADSP-BF532
The time for the voltage on the bus to decay by ∆V is dependent
on the capacitive load CL and the load current II. This decay time
can be approximated by the equation:
POWER DISSIPATION
Many operating conditions can affect power dissipation. System
designers should refer to EE-229: Estimating Power for
ADSP-BF531/ADSP-BF532/ADSP-BF533 Blackfin Processors on
the Analog Devices website (www.analog.com)—use site search
on “EE-229.” This document provides detailed information for
optimizing your design for lowest power.
tDECAY = (CL∆V) ⁄ IL
The time tDECAY is calculated with test loads CL and IL, and with
∆V equal to 0.1 V for VDDEXT (nominal) = 1.8 V or 0.5 V for
V
DDEXT (nominal) = 2.5 V/3.3 V.
See the ADSP-BF53x Blackfin Processor Hardware Reference
Manual for definitions of the various operating modes and for
instructions on how to minimize system power.
The time tDIS_MEASURED is the interval from when the reference
signal switches, to when the output voltage decays ∆V from the
measured output high or output low voltage.
TEST CONDITIONS
Example System Hold Time Calculation
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section. Figure 40
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point VMEAS is 0.95 V for
VDDEXT (nominal) = 1.8 V, and 1.5 V for
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-BF531/ADSP-BF532
processor’s output voltage and the input threshold for the
device requiring the hold time. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be tDECAY plus the various out-
put disable times as specified in the Timing Specifications on
Page 23 (for example tDSDAT for an SDRAM write cycle as shown
in SDRAM Interface Timing on Page 27).
V
DDEXT (nominal) = 2.5 V/3.3 V.
INPUT
OR
OUTPUT
VMEAS
VMEAS
Figure 40. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
REFERENCE
SIGNAL
Output Enable Time Measurement
tDIS_MEASURED
tENA_MEASURED
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
tDIS
tENA
VOH
VOH(MEASURED)
(MEASURED)
VOH (MEASURED) ؊⌬V
VOL (MEASURED) + ⌬V
VTRIP(HIGH)
VTRIP(LOW)
The output enable time tENA is the interval from the point when a
reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
Figure 41.
VOL
VOL(MEASURED)
(MEASURED)
tDECAY
tTRIP
The time tENA MEASURED is the interval, from when the reference sig-
nal switches,_to when the output voltage reaches VTRIP(high) or
VTRIP (low). For VDDEXT (nominal) = 1.8 V—VTRIP (high) is 1.3 V
and VTRIP (low) is 0.7 V. For VDDEXT (nominal) = 2.5 V/3.3 V—
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE
V
TRIP (high) is 2.0 V and VTRIP (low) is 1.0 V . Time tTRIP is the
Figure 41. Output Enable/Disable
interval from when the output starts driving to when the output
reaches the VTRIP (high) or VTRIP (low) trip voltage.
50⍀
TO
OUTPUT
PIN
V
LOAD
Time tENA is calculated as shown in the equation:
tENA = tENA_MEASURED – tTRIP
30pF
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time tDIS is the
difference between tDIS_MEASURED and tDECAY as shown on the left
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 42). VLOAD is 0.95 V for VDDEXT
(nominal) = 1.8 V, and 1.5 V for VDDEXT (nominal) =
2.5 V/3.3 V. Figure 43 on Page 46 through Figure 54 on Page 48
show how output rise time varies with capacitance. The delay
side of Figure 40.
tDIS = tDIS_MEASURED – tDECAY
Rev. D
|
Page 45 of 60
|
August 2006
ADI [ ADI ]
