ADSP-BF531/ADSP-BF532
SCK (66MHz DRIVER), VDDEXT (MAX) = 3.65V
TMR0 (33MHz DRIVER), VDDEXT (MAX) = 3.65V
14
20
18
12
10
8
16
RISE TIME
RISE TIME
14
12
FALL TIME
FALL TIME
10
8
6
4
2
0
6
4
2
0
0
50
100
150
200
250
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
Figure 54. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at VDDEXT = 3.65 V
Figure 51. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver C at VDDEXT = 3.65 V
ENVIRONMENTAL CONDITIONS
SCK (66MHz DRIVER), V
DDEXT
= 1.7V
18
16
14
12
10
8
To determine the junction temperature on the application
printed circuit board use:
RISE TIME
TJ = TCASE + (ΨJT × PD)
where:
FALL TIME
TJ = junction temperature (؇C).
T
CASE = case temperature (؇C) measured by customer at top
center of package.
6
ΨJT = from Table 30 through Table 32.
4
PD = power dissipation (see Power Dissipation on Page 45 for
the method to calculate PD).
2
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 52. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at VDDEXT = 1.8 V
TJ = TA + (θJA × PD)
where:
TA = ambient temperature (؇C).
SCK (66MHz DRIVER), VDDEXT (MIN) = 2.25V
18
In Table 30 through Table 32, airflow measurements comply
with JEDEC standards JESD51–2 and JESD51–6, and the junc-
tion-to-board measurement complies with JESD51–8. The
junction-to-case measurement complies with MIL-STD-883
(Method 1012.1). All measurements use a 2S2P JEDEC test
board.
16
14
RISE TIME
12
10
FALL TIME
8
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 53. Typical Rise and Fall Times (10% to 90%) versus Load Capacitance
for Driver D at VDDEXT = 2.25 V
Rev. D
|
Page 48 of 60
|
August 2006
ADI [ ADI ]
