ADSP-BF531/ADSP-BF532
Timer Cycle Timing
Table 28 and Figure 26 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of fSCLK/2 MHz.
Table 28. Timer Cycle Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Parameter
Min Max
Min
Max
Unit
Timing Characteristics
tWL
Timer Pulse Width Input Low1 (Measured in SCLK Cycles)
1
1
1
1
SCLK
SCLK
tWH Timer Pulse Width Input High1 (Measured in SCLK Cycles)
Switching Characteristic
tHTO Timer Pulse Width Output2 (Measured in SCLK Cycles)
1
(232–1)
1
(232–1)
SCLK
1 The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2 The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tHTO
TMRx
(PWM OUTPUT MODE)
TMRx
tWL
tWH
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
Figure 26. Timer PWM_OUT Cycle Timing
Rev. D
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Page 41 of 60
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August 2006
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