ADSP-BF531/ADSP-BF532
Serial Peripheral Interface (SPI) Port
—Master Timing
Table 25 and Figure 22 describe SPI port master operations.
Table 25. Serial Peripheral Interface (SPI) Port—Master Timing
VDDEXT = 1.8 V VDDEXT = 2.5 V/3.3 V
Parameter
Min
Max Min
Max Unit
Timing Requirements
tSSPIDM
tHSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
8.5
7.5
ns
ns
–1.5
–1.5
Switching Characteristics
tSDSCIM
tSPICHM
tSPICLM
tSPICLK
SPISELx Low to First SCK Edge (x=0 or x=1)
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
2tSCLK –1.5
ns
ns
ns
ns
ns
ns
Serial Clock High Period
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
Serial Clock Low Period
Serial Clock Period
tHDSM
Last SCK Edge to SPISELx High (x=0 or x=1)
Sequential Transfer Delay
tSPITDM
tDDSPIDM
tHDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
6
6
ns
ns
–1.0
+4.0 –1.0
+4.0
SPISELx
(OUTPUT)
tSPICLK
tHDSM
tSPITDM
tSDSCIM
tSPICHM
tSPICLM
SCK
(CPOL = 0)
(OUTPUT)
tSPICLM
tSPICHM
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
tHDSPIDM
MOSI
(OUTPUT)
MSB
LSB
CPHA = 1
tSSPIDM
tHSPIDM
tSSPIDM
tHSPIDM
MISO
(INPUT)
MSB VALID
LSB VALID
tDDSPIDM
tHDSPIDM
MOSI
(OUTPUT)
MSB
LSB
CPHA = 0
tSSPIDM
tHSPIDM
MISO
(INPUT)
MSB VALID
LSB VALID
Figure 22. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. D
|
Page 37 of 60
|
August 2006
ADI [ ADI ]
