ADSP-BF531/ADSP-BF532
PIN DESCRIPTIONS
ADSP-BF531/ADSP-BF532 processor pin definitions are listed
in Table 9.
If BR is active, then the memory pins are also three-stated. All
unused I/O pins have their input buffers disabled with the
exception of the pins that need pull-ups or pull-downs as noted
in the table footnotes.
All pins are three-stated during and immediately after reset,
except the memory interface, asynchronous memory control,
and synchronous memory control pins, which are driven high.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some pins have dual, multiplexed
functionality. In cases where pin functionality is reconfigurable,
the default state is shown in plain text, while alternate function-
ality is shown in italics.
Table 9. Pin Descriptions
Driver
Pin Name
Type Function
Type1 Pull-Up/Down Requirement
Memory Interface
ADDR19–1
O
Address Bus for Async/Sync Access
A
A
None
DATA15–0
I/O Data Bus for Async/Sync Access
None
ABE1–0/SDQM1–0
O
I
Byte Enables/Data Masks for Async/Sync Access A
None
BR
Bus Request
Bus Grant
Pull-up Required If Function Not Used
BG
O
O
A
A
None
None
BGH
Bus Grant Hang
Asynchronous Memory Control
AMS3–0
O
I
Bank Select
A
None
ARDY
Hardware Ready Control
Output Enable
Read Enable
Pull-up Required If Function Not Used
AOE
O
O
O
A
A
A
None
None
None
ARE
AWE
Write Enable
Synchronous Memory Control
SRAS
SCAS
O
O
O
O
O
O
O
Row Address Strobe
Column Address Strobe
Write Enable
A
A
A
A
B
None
None
None
None
None
None
None
SWE
SCKE
Clock Enable
CLKOUT
SA10
Clock Output
A10 Pin
A
A
SMS
Bank Select
Timers
TMR0
I/O Timer 0
C
C
C
None
None
None
TMR1/PPI_FS1
TMR2/PPI_FS2
I/O Timer 1/PPI Frame Sync1
I/O Timer 2/PPI Frame Sync2
Rev. D
|
Page 17 of 60
|
August 2006
ADI [ ADI ]
