ADSP-BF531/ADSP-BF532
BOOTING MODES
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
The ADSP-BF531/ADSP-BF532 processor has two mechanisms
(listed in Table 8) for automatically loading internal L1 instruc-
tion memory after a reset. A third mode is provided to execute
from external memory, bypassing the boot sequence.
÷ 1, 2, 4, 8
CCLK
SCLK
PLL
0.5× to 64×
CLKIN
VCO
Table 8. Booting Modes
÷ 1 to 15
BMODE1–0
Description
00
Executefrom16-bitexternalmemory(bypass
boot ROM)
SCLK ≤ CCLK
SCLK ≤ 133 MHz
01
10
11
Boot from 8-bit or 16-bit FLASH
Boot from SPI host slave mode
Figure 8. Frequency Modification Methods
Boot from SPI serial EEPROM (8-, 16-, or 24-bit
address range)
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
Table 6. Example System Clock Ratios
• Execute from 16-bit external memory – Execution starts
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
Example Frequency Ratios
(MHz)
VCO
100
Signal Name Divider Ratio
SSEL3–0
VCO/SCLK
SCLK
100
0001
1:1
3:1
0011
400
133
• Boot from 8-bit or 16-bit external flash memory – The flash
boot routine located in boot ROM memory space is set up
using asynchronous memory bank 0. All configuration set-
tings are set for the slowest device possible (3-cycle hold
time; 15-cycle R/W access times; 4-cycle setup).
The maximum frequency of the system clock is fSCLK. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of fSCLK. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
• Boot from SPI serial EEPROM (8-, 16-, or 24-bit
addressable) – The SPI uses the PF2 output pin to select a
single SPI EEPROM device, submits successive read com-
mands at addresses 0x00, 0x0000, and 0x000000 until a
valid 8-, 16-, or 24-bit addressable EEPROM is detected,
and begins clocking data into the beginning of L1 instruc-
tion memory.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 7. This programmable core clock capability is useful for
fast core frequency modifications.
For each of the boot modes, a 10-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
Table 7. Core Clock Ratios
Example Frequency Ratios
(MHz)
Signal Name Divider Ratio
CSEL1–0
VCO/CCLK
VCO
300
300
400
200
CCLK
300
150
100
25
00
01
10
11
1:1
2:1
4:1
8:1
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
Rev. D
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Page 14 of 60
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August 2006
ADI [ ADI ]
