ADSP-BF531/ADSP-BF532
Serial Peripheral Interface (SPI) Port
—Slave Timing
and
describe SPI port slave operations.
Table 26. Serial Peripheral Interface (SPI) Port—Slave Timing
V
DDEXT
= 1.8 V
Min
Max
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
1.6
1.6
0
0
0
0
9
9
10
10
V
DDEXT
= 2.5 V/3.3 V
Min
Max
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
1.6
1.6
0
0
0
0
8
8
10
10
Parameter
Timing Requirements
t
SPICHS
Serial Clock High Period
Serial Clock Low Period
t
SPICLS
t
SPICLK
Serial Clock Period
t
HDS
Last SCK Edge to SPISS Not Asserted
t
SPITDS
Sequential Transfer Delay
t
SDSCI
SPISS Assertion to First SCK Edge
t
SSPID
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
t
HSPID
Switching Characteristics
t
DSOE
SPISS Assertion to Data Out Active
t
DSDHI
SPISS Deassertion to Data High Impedance
t
DDSPID
SCK Edge to Data Out Valid (Data Out Delay)
t
HDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPISS
(INPUT)
t
SPICHS
SCK
(CPOL = 0)
(INPUT)
t
SPICLS
t
SPICLK
t
HDS
t
SPITDS
t
SDSCI
SCK
(CPOL = 1)
(INPUT)
t
SPICLS
t
SPICHS
t
DSOE
t
DDSPID
t
HDSPID
t
DDSPID
t
DSDHI
LSB
MISO
(OUTPUT)
CPHA = 1
MOSI
(INPUT)
MSB
t
SSPID
MSB VALID
t
HSPID
t
SSPID
t
HSPID
LSB VALID
t
DSOE
MISO
(OUTPUT)
CPHA = 0
MOSI
(INPUT)
t
DDSPID
MSB
LSB
t
DSDHI
t
HSPID
t
SSPID
MSB VALID
LSB VALID
Figure 23. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. D |
Page 38 of 60 |
August 2006
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