ADSP-BF531/ADSP-BF532
Serial Peripheral Interface (SPI) Port
—Master Timing
and
describe SPI port master operations.
Table 25. Serial Peripheral Interface (SPI) Port—Master Timing
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min
Max Min
Max
8.5
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
0
6
–1.0
+4.0
7.5
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
0
–1.0
Parameter
Timing Requirements
t
SSPIDM
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
t
HSPIDM
Switching Characteristics
t
SDSCIM
SPISELx Low to First SCK Edge (x=0 or x=1)
t
SPICHM
Serial Clock High Period
t
SPICLM
Serial Clock Low Period
t
SPICLK
Serial Clock Period
Last SCK Edge to SPISELx High (x=0 or x=1)
t
HDSM
t
SPITDM
Sequential Transfer Delay
t
DDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)
t
HDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)
SPISELx
(OUTPUT)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
+4.0
t
SDSCIM
SCK
(CPOL = 0)
(OUTPUT)
t
SPICHM
t
SPICLM
t
SPICLK
t
HDSM
t
SPITDM
t
SPICLM
SCK
(CPOL = 1)
(OUTPUT)
t
SPICHM
t
DDSPIDM
MOSI
(OUTPUT)
CPHA = 1
MISO
(INPUT)
MSB
t
HDSPIDM
LSB
t
SSPIDM
MSB VALID
t
HSPIDM
t
SSPIDM
LSB VALID
t
HSPIDM
t
DDSPIDM
MOSI
(OUTPUT)
CPHA = 0
MSB
t
HDSPIDM
LSB
t
SSPIDM
MISO
(INPUT)
MSB VALID
t
HSPIDM
LSB VALID
Figure 22. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. D |
Page 37 of 60 |
August 2006
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