ADSP-BF531/ADSP-BF532
Clock and Reset Timing
and
describe clock and reset operations. Per
combinations of
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 400 MHz/133 MHz.
Table 15. Clock and Reset Timing
Parameter
Timing Requirements
t
CKIN
CLKIN Period
t
CKINL
CLKIN Low Pulse
2
CLKIN High Pulse
1
t
CKINH
t
WRST
RESET Asserted Pulse Width Low
3
1
2
Min
25.0
10.0
10.0
11 t
CKIN
Max
100.0
1
Unit
ns
ns
ns
ns
If DF bit in PLL_CTL register is set, then the maximum t
CKIN
period is 50 ns.
Applies to bypass mode and nonbypass mode.
3
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2,000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
t
CKIN
CLKIN
t
CKINL
RESET
t
CKINH
t
WRST
Figure 10. Clock and Reset Timing
Rev. D |
Page 24 of 60 |
August 2006
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