ADSP-BF531/ADSP-BF532
External Port Bus Request and Grant Cycle Timing
and
describe external port bus request and
bus grant operations.
Table 19. External Port Bus Request and Grant Cycle Timing
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Min Max Min
Max
Unit
4.6
1.0
4.5
4.5
4.6
4.6
4.6
4.6
4.6
0.0
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Timing Requirements
t
BS
BR Asserted to CLKOUT High Setup
t
BH
CLKOUT High to BR Deasserted Hold Time
Switching Characteristics
CLKOUT Low to xMS, Address, and RD/WR Disable
t
SD
t
SE
CLKOUT Low to xMS, Address, and RD/WR Enable
t
DBG
CLKOUT High to BG High Setup
t
EBG
CLKOUT High to BG Deasserted Hold Time
t
DBH
CLKOUT High to BGH High Setup
t
EBH
CLKOUT High to BGH Deasserted Hold Time
CLKOUT
t
BS
BR
t
BH
t
SD
AMSx
t
SE
t
SD
t
SE
ADDR19-1
ABE1-0
t
SD
t
SE
AWE
ARE
t
DBG
BG
t
EBG
t
DBH
BGH
t
EBH
Figure 14. External Port Bus Request and Grant Cycle Timing
Rev. D |
Page 28 of 60 |
August 2006
AD [ ANALOG DEVICES ]
