ADSP-21061/ADSP-21061L
Capacitive Loading
Example System Hold Time Calculation
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 25). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 28–29,
32–33 show how output rise time varies with capacitance. Fig-
ures 30, 34 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time under Test Conditions.) The graphs of
Figures 28, 29 and 30 may not be linear outside the ranges
shown.
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ∆V
to be the difference between the ADSP-2106x’s output voltage
and the input threshold for the device requiring the hold time. A
typical ∆V will be 0.4 V. CL is the total bus capacitance (per
data line), and IL is the total leakage or three-state current (per
data line). The hold time will be tDECAY plus the minimum
disable time (i.e., tDATRWH for the write cycle).
REFERENCE
SIGNAL
INPUT OR
OUTPUT
tMEASURED
1.5V
1.5V
tENA
tDIS
V
Figure 26. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
OH (MEASURED)
V
V
OH (MEASURED)
V
V
– ⌬V
+ ⌬V
2.0V
1.0V
OH (MEASURED)
OUTPUT
OL (MEASURED)
V
OL (MEASURED)
OL (MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
Figure 24. Output Enable/Disable
I
OL
TO
OUTPUT
PIN
+1.5V
50pF
I
OH
Figure 25. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
REV. B
–39–
ADI [ ADI ]
