ADSP-21061/ADSP-21061L
DATA RECEIVE– INTERNAL CLOCK
DATA RECEIVE– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
RCLK
RCLK
tDFSE
tHOFSE
tDFSE
tHOFSE
tHFSE
tSFSI
tHFSI
tSFSE
RFS
DR
RFS
DR
tSDRE
tHDRE
tSDRI
tHDRI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT– INTERNAL CLOCK
DATA TRANSMIT– EXTERNAL CLOCK
SAMPLE
EDGE
DRIVE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKW
TCLK
TCLK
tDFSI
tHOFSI
tDFSE
tHOFSE
tSFSI
tHFSI
tHFSE
tSFSE
TFS
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TCLK (EXT)
TFS ("LATE" EXT)
TCLK / RCLK
tDDTEN
tDDTTE
DT
DRIVE
EDGE
DRIVE
EDGE
TCLK (INT)
TFS ("LATE", INT)
TCLK / RCLK
tDDTIN
tDDTTI
DT
CLKIN
tDPTR
SPORT ENABLE AND
THREE-STATE
LATENCY
TCLK, RCLK
TFS, RFS, DT
SPORT DISABLE DELAY
FROM INSTRUCTION
IS TWO CYCLES
tDCLK
TCLK (INT)
RCLK (INT)
LOW TO HIGH ONLY
Figure 21. Serial Ports
REV. B
–35–
ADI [ ADI ]
