ADSP-21061/ADSP-21061L
JTAG Test Access Port and Emulation
ADSP-21061 (5 V)
ADSP-21061L (3.3 V)
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tTCK
TCK Period
tCK
tCK
6
7
18
tCK
tCK
6
7
18
ns
ns
ns
ns
ns
ns
tSTAP
tHTAP
tSSYS
tHSYS
TDI, TMS Setup before TCK High
TDI, TMS Hold after TCK High
System Inputs Setup before TCK Low1
System Inputs Hold after TCK Low1
tTRSTW TRST Pulsewidth
4tCK
4tCK
Switching Characteristics:
tDTDO
tDSYS
TDO Delay from TCK Low
13
18.5
13
18.5
ns
ns
System Outputs Delay after TCK Low2
NOTES
1System Inputs = DATA47-0, ADDR31-0, RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA, IRQ2-0, FLAG3-0, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, EBOOT, LBOOT, BMS, CLKIN, RESET.
2System Outputs = DATA47-0, ADDR31-0, MS3-0, RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR6-1, CPA, FLAG3-0, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, BMS.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tSSYS
tHSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 23. JTAG Test Access Port and Emulation
REV. B
–37–
ADI [ ADI ]
