ADSP-21061/ADSP-21061L
Asynchronous Read/Write—Host to ADSP-21061
drive the RD and WR pins to access the ADSP-21061’s internal
memory or IOP registers. HBR and HBG are assumed low for
this timing.
Use these specifications for asynchronous host processor accesses
of an ADSP-21061, after the host has asserted CS and HBR
(low). After HBG is returned by the ADSP-21061, the host can
ADSP-21061 (5 V)
Max
ADSP-21061L (3.3 V)
Parameter
Min
Min
Max
Unit
Read Cycle
Timing Requirements:
tSADRDL
tHADRDH
tWRWH
Address Setup/CS Low before RD Low1
Address Hold/CS Hold Low after RD
RD/WR High Width
0
0
6
0
0
0
0
6
0
0
ns
ns
ns
ns
ns
tDRDHRDY
tDRDHRDY
RD High Delay after REDY (O/D) Disable
RD High Delay after REDY (A/D) Disable
Switching Characteristics:
tSDATRDY
tDRDYRDL
tRDYPRD
Data Valid before REDY Disable from Low
2
2
ns
ns
ns
ns
REDY (O/D) or (A/D) Low Delay after RD Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable after RD High
10
13.5
8
45 + DT
2
45 + DT
2
tHDARWH
8
Write Cycle
Timing Requirements:
tSCSWRL
tHCSWRH
tSADWRH
tHADWRH
tWWRL
tWRWH
tDWRHRDY
CS Low Setup before WR Low
CS Low Hold after WR High
Address Setup before WR High
Address Hold after WR High
WR Low Width
RD/WR High Width
WR High Delay after REDY (O/D) or (A/D) Disable
Data Setup before WR High
0
0
5
2
8
6
0
3
0
0
5
2
8
6
0
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSDATWH
tSDATWH (50 MHz) Data Setup before WR High, tCK = 20 ns2
2.5
1
tHDATWH
Data Hold after WR High
1
Switching Characteristics:
tDRDYWRL
tRDYPWR
tSRDYCK
REDY (O/D) or (A/D) Low Delay after WR/CS Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
REDY (O/D) or (A/D) Disable to CLKIN
11
13.5
ns
ns
15
15
1 + 7DT/16
8 + 7DT/16 1 + 7DT/16
8 + 7DT/16 ns
NOTES
1Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD
or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Proces-
sor Control of the ADSP-2106x section in the ADSP-2106x SHARC User’s Manual, Second Edition.
2This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at tCK < 25 ns. For all other devices, use the preceding timing specification of the
same name.
CLKIN
tSRDYCK
REDY (O/D)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18a. Synchronous REDY Timing
REV. B
–28–
ADI [ ADI ]
