ADSP-21061/ADSP-21061L
Synchronous Read/Write—Bus Slave
Use these specifications for ADSP-21061 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave)
timing requirements.
ADSP-21061 (5 V)
ADSP-21061L (3.3 V)
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tSADRI
tHADRI
tSRWLI
tHRWLI
tHRWLI
Address, SW Setup before CLKIN
14 + DT/2
14 + DT/2
ns
ns
ns
ns
Address, SW Hold before CLKIN
RD/WR Low Setup before CLKIN1
RD/WR Low Hold after CLKIN
RD/WR Low Hold after CLKIN
44 MHz/50 MHz2
RD/WR Pulse High
Data Setup before WR High
Data Hold after WR High
5 + DT/2
5 + DT/2
8.5 + 5DT/16
–4 – 5DT/16
8.5 + 5DT/16
–4 – 5DT/16
8 + 7DT/16
8 + 7DT/16
8 + 7DT/16
8 + 7DT/16
–3.5 – 5DT/16
–3.5 – 5DT/16
ns
ns
ns
ns
tRWHPI
tSDATWH
tHDATWH
3
3
1
3
3
1
Switching Characteristics:
tSDDATO
tDATTR
tDACKAD
tACKTR
Data Delay after CLKIN
19 + 5DT/16
7 – DT/8
8
19 + 5DT/16
7 – DT/8
8
ns
ns
ns
ns
Data Disable after CLKIN3
ACK Delay after Address, SW4
ACK Disable after CLKIN4
0 – DT/8
0 – DT/8
–1 – DT/8
6 – DT/8
–1 – DT/8
6 – DT/8
NOTES
1tSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t SRWLI (min)
= 4 + DT/8.
2This specification applies to the ADSP-21061LKS-176 (3.3 V, 44 MHz) and the ADSP-21061KS-200 (5 V, 50 MHz), o perating at tCK <25 ns. For all other devices,
use the preceding timing specification of the same name.
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
4tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT/4, then ACK is valid 15.5 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with tACKTR
.
CLKIN
tSADRI
tHADRI
ADDRESS
SW
tDACKAD
tACKTR
ACK
READ ACCESS
tSRWLI
tHRWLI
tRWHPI
RD
tSDDATO
tDATTR
DATA
(OUT)
WRITE ACCESS
tRWHPI
tSRWLI
tHRWLI
WR
tHDATWH
tSDATWH
DATA
(IN)
REV. B
–25–
ADI [ ADI ]
