ADSP-21061/ADSP-21061L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
ADSP-21061 (5 V)
ADSP-21061L (3.3 V)
Parameter
Min
Max
Min
Max
Unit
Timing Requirements:
tSTSCK
tHTSCK
SBTS Setup before CLKIN
SBTS Hold before CLKIN
12 + DT/2
12 + DT/2
ns
ns
6 + DT/2
6 + DT/2
Switching Characteristics:
tMIENA
tMIENS
tMIENHG
tMITRA
Address/Select Enable after CLKIN
–1 – DT/8
–1.5 – DT/8
–1.5 – DT/8
–1 – DT/8
–1.5 – DT/8
–1.5 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Strobes Enable after CLKIN1
HBG Enable after CLKIN
Address/Select Disable after CLKIN
Strobes Disable after CLKIN1
HBG Disable after CLKIN
0 – DT/4
1.5 – DT/4
2 – DT/4
0 – DT/4
1.5 – DT/4
2 – DT/4
tMITRS
tMITRHG
tDATEN
tDATTR
tACKEN
tACKTR
tADCEN
tADCTR
tMTRHBG
tMENHBG
Data Enable after CLKIN2
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
Data Disable after CLKIN2
7 – DT/8
6 – DT/8
8 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
ACK Enable after CLKIN2
ACK Disable after CLKIN2
ADRCLK Enable after CLKIN
ADRCLK Disable after CLKIN
Memory Interface Disable before HBG Low3
Memory Interface Enable after HBG High3
0 + DT/8
19 + DT
0 + DT/8
19 + DT
NOTES
1Strobes = RD, WR, MSx, SW, PAGE, DMAG, BMS.
2In addition to bus master transition cycles, these specifications also apply to bus master and bus slave synchronous read/write.
3Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
REV. B
–30–
ADI [ ADI ]
