ADSP-21061/ADSP-21061L
Synchronous Read/Write—Bus Master
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-21061 must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-21061 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes (see Memory Read—
Bus Master and Memory Write—Bus Master).
ADSP-21061 (5 V)
ADSP-21061L (3.3 V)
Max
Parameter
Min
Max
Min
Unit
Timing Requirements:
tSSDATI
Data Setup before CLKIN
2 + DT/8
2 + DT/8
ns
tSSDATI (50 MHz) Data Setup before CLKIN,
tCK = 20 ns1
1.5 + DT/8
3.5 – DT/8
ns
ns
tHSDATI
tDAAK
Data Hold after CLKIN
ACK Delay after Address, MSx,
SW, BMS2, 3
3.5 – DT/8
15 + 7 DT/8 + W
6.5 – DT/8
15 + 7 DT/8 + W
6.5 – DT/8
ns
ns
ns
tSACKC
tHACK
ACK Setup before CLKIN2
ACK Hold after CLKIN
6.5 + DT/4
–1 – DT/4
6.5 + DT/4
–1 – DT/4
Switching Characteristics:
tDADRO
Address, MSx, BMS, SW Delay
after CLKIN2
ns
tHADRO
Address, MSx, BMS, SW Hold
after CLKIN
–1 – DT/8
9 + DT/8
–1.5 – DT/8
–2.5 – 3DT/16
–1 – DT/8
9 + DT/8
–1.5 – DT/8
–2.5 – 3DT/16
ns
ns
ns
ns
tDPGC
tDRDO
tDWRO
PAGE Delay after CLKIN
RD High Delay after CLKIN
WR High Delay after CLKIN
16 + DT/8
4 – DT/8
4 – 3DT/16
16 + DT/8
4 – DT/8
4 – 3DT/16
tDWRO (50 MHz) WR High Delay after CLKIN,
tCK = 20 ns1
RD/WR Low Delay after CLKIN 8 + DT/4
Data Delay after CLKIN
Data Disable after CLKIN4
ADRCLK Delay after CLKIN
ADRCLK Period
–1.5 – 3DT/16
4 – 3DT/16
12 + DT/4
19 + 5DT/16
7 – DT/8
ns
ns
ns
ns
ns
ns
ns
ns
tDRWL
8 + DT/4
12 + DT/4
19 + 5DT/16
7 – DT/8
tSDDATO
tDATTR
tDADCCK
tADRCK
tADRCKH
tADRCKL
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
0 – DT/8
4 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
10 + DT/8
10 + DT/8
ADRCLK Width High
ADRCLK Width Low
W = (number of Wait states specified in WAIT register) × tCK
.
NOTES
1This specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at tCK < 25 ns. For all other devices, use the preceding timing specification of the
same name.
2ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).
3Data Hold: User must meet tHDA or tHDRH or synchronous specification tHDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold
times given capacitive and dc loads.
4See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
REV. B
–23–
ADI [ ADI ]
