ADSP-21061/ADSP-21061L
ADSP-21061 (5 V)
40 MHz
Min
33 MHz
Max
50 MHz
Min
Parameter
Min
Max
Max
Unit
Clock Input
Timing Requirements:
tCK
CLKIN Period
30
7
5
100
3
25
7
5
100
3
20
7
5
100
3
ns
ns
ns
ns
tCKL
tCKH
tCKRF
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
ADSP-21061L (3.3 V)
40 MHz
44 MHz
Parameter
Min
Max
Min
Max
Unit
Clock Input
Timing Requirements:
tCK
CLKIN Period
25
7
5
100
3
22.5
7
5
100
3
ns
ns
ns
ns
tCKL
tCKH
tCKRF
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
tCK
CLKIN
tCKH
tCKL
Figure 8. Clock Input
ADSP-21061 (5 V)
ADSP-21061L (3.3 V)
Parameter
Reset
Min
Max
Min
Max
Unit
Timing Requirements:
tWRST
RESET Pulsewidth Low1
tSRST
RESET Setup before CLKIN High2
4tCK
14 + DT/2
4tCK
14 + DT/2
ns
ns
tCK
tCK
NOTES
1Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
2Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
CLKIN
tSRST
tWRST
RESET
Figure 9. Reset
ADSP-21061 (5 V)
ADSP-21061L (3.3 V)
Parameter
Min
Max
Min
Max
Unit
Interrupts
Timing Requirements:
tSIR
tHIR
tIPW
IRQ2-0 Setup before CLKIN High1
18 + 3DT/4
2 + tCK
18 + 3DT/4
2 + tCK
ns
ns
ns
IRQ2-0 Hold before CLKIN High1
IRQ2-0 Pulsewidth2
12 + 3DT/4
12 + 3DT/4
NOTES
1Only required for IRQx recognition in the following cycle.
2Applies only if tSIR and tHIR requirements are not met.
REV. B
–19–
ADI [ ADI ]
