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ADSP-21061LKB-160 参数 Datasheet PDF下载

ADSP-21061LKB-160图片预览
型号: ADSP-21061LKB-160
PDF下载: 下载PDF文件 查看货源
内容描述: ADSP- 2106x SHARC DSP单片机系列 [ADSP-2106x SHARC DSP Microcomputer Family]
分类和应用: 外围集成电路时钟
文件页数/大小: 47 页 / 366 K
品牌: ADI [ ADI ]
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ADSP-21061/ADSP-21061L  
Pin  
Type  
Function  
TFSx  
RFSx  
EBOOT  
I/O  
I/O  
I
Transmit Frame Sync (Serial Ports 0, 1).  
Receive Frame Sync (Serial Ports 0, 1).  
EPROM Boot Select. When EBOOT is high, the ADSP-21061 is configured for booting from an 8-  
bit EPROM. When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See table  
below. This signal is a system configuration selection which should be hardwired.  
LBOOT  
I
Link Boot—Must be tied to GND.  
BMS  
I/O/T*  
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,  
LBOOT = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indi-  
cates that no booting will occur and that ADSP-21061 will begin executing instructions from external  
memory. See table below. This input is a system configuration selection which should be hardwired.  
*Three-statable only in EPROM boot mode (when BMS is an output).  
EBOOT  
LBOOT  
BMS  
Booting Mode  
1
0
0
0
0
0
Output  
1 (Input)  
0 (Input)  
EPROM (Connect BMS to EPROM chip select.)  
Host Processor  
No Booting. Processor executes from external memory.  
CLKIN  
I
Clock In. External clock input to the ADSP-21061. The instruction cycle rate is equal to CLKIN.  
CLKIN may not be halted, changed, or operated below the specified frequency.  
RESET  
I/A  
Processor Reset. Resets the ADSP-21061 to a known state and begins execution at the program  
memory location specified by the hardware reset vector address. This input must be asserted (low) at  
power-up.  
TCK  
TMS  
I
I/S  
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.  
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kinternal pull-up  
resistor.  
TDI  
I/S  
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kinternal  
pull-up resistor.  
TDO  
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.  
TRST  
I/A  
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-  
up or held low for proper operation of the ADSP-21061. TRST has a 20 kinternal pull-up resistor.  
EMU  
ICSA  
VDD  
GND  
NC  
O
O
P
Emulation Status. Must be connected to the ADSP-21061 EZ-ICEtarget board connector only.  
Reserved, leave unconnected.  
Power Supply; nominally +3.3 V dc for ADSP-21061L, +5.0 V dc for ADSP-21061.  
Power Supply Return.  
Do Not Connect. Reserved pins which must be left open and unconnected.  
G
REV. B  
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