ADE7761A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
V
20
19
18
17
16
15
14
13
12
11
F1
DD
V
V
V
V
F2
1A
1B
1N
2N
CF
DGND
REVP
FAULT
RCLKIN
PGA
S0
ADE7761A
TOP VIEW
(Not to Scale)
V
2P
MISCAL
AGND
REF
IN/OUT
SCF 10
S1
Figure 3. Pin Configuration (SSOP)
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
VDD
Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7761A. The supply voltage
should be maintained at 5 V 5% for specified operation. This pin should be decoupled with a 10 μF capacitor
in parallel with a ceramic 100 nF capacitor.
2, 3
V1A, V1B
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with maximum
differential input signal levels of 660 mV with respect to V1N for specified operation. The maximum signal level
at these pins is 1 V with respect to AGND. Both inputs have internal ESD protection circuitry, and an overvoltage
of 6 V can also be sustained on these inputs without risk of permanent damage.
4
5
6
7
V1N
Negative Input for Differential Voltage Inputs, V1A and V1B. The maximum signal level at this pin is 1 V with
respect to AGND. The input has internal ESD protection circuitry, and an overvoltage of 6 V can also be sustained
on this input without risk of permanent damage. The input should be directly connected to the burden resistor
and held at a fixed potential, that is, AGND. See the Analog Inputs section.
Negative Input for Differential Voltage Inputs, V2P and MISCAL. The maximum signal level at this pin is 1 V with
respect to AGND. The input has internal ESD protection circuitry, and an overvoltage of 6 V can also be sustained
on this input without risk of permanent damage. The input should be held at a fixed potential, that is, AGND. See
the Analog Inputs section.
Analog Input for Channel 2 (Voltage Channel). This input is a fully differential voltage input with maximum
differential input signal levels of 660 mV with respect to V2N for specified operation. The maximum signal level at
this pin is 1 V with respect to AGND. This input has internal ESD protection circuitry, and an overvoltage of 6 V
can also be sustained on this input without risk of permanent damage.
Analog Input for Missing Neutral Calibration. This pin can be used to calibrate the CF-F1-F2 frequencies in the
missing neutral condition. This input is a fully differential voltage input with maximum differential input signal
levels of 660 mV with respect to V2N for specified operation. The maximum signal level at this pin is 1 V with
respect to AGND. This input has internal ESD protection circuitry, and an overvoltage of 6 V can also be
sustained on this input without risk of permanent damage.
V2N
V2P
MISCAL
8
9
AGND
This pin provides the ground reference for the analog circuitry in the ADE7761A, that is, ADCs and reference. This
pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground reference for all
analog circuitry, such as antialiasing filters, and current and voltage transducers. For good noise suppression, the
analog ground plane should be connected only to the digital ground plane at the DGND pin.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
2.5 V 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be
connected at this pin. In either case, this pin should be decoupled to AGND with a 1 ꢀF ceramic capacitor and
100 nF ceramic capacitor.
REFIN/OUT
10
SCF
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF.
Table 7 shows how the calibration frequencies are selected.
11, 12
S1, S0
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.
This offers the designer greater flexibility when designing the energy meter. See the Selecting a Frequency for an
Energy Meter Application section.
13
14
PGA
RCLKIN
This logic input is used to select the gain for the analog inputs, V1A and V1B. The possible gains are 1 and 16.
To enable the internal oscillator as a clock source on the chip, a precise low temperature drift resistor at
nominal value of 6.2 kΩ must be connected from this pin to DGND.
Rev. 0 | Page 6 of 24
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