ADE7761A
Parameter
LOGIC INPUTS5
Value
Unit
Test Conditions/Comments
PGA, SCF, S1, and S0
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS5
CF, REVP, and FAULT
Output High Voltage, VOH
Output Low Voltage, VOH
F1 and F2
2.4
0.8
3
V, min
VDD = 5 V 5%
VDD = 5 V 5%
Typical 10 nA, VIN = 0 V to VDD
V, max
μA, max
pF, max
10
4
1
V, min
V, max
VDD = 5 V 5%
VDD = 5 V 5%
Output High Voltage, VOH
Output Low Voltage, VOH
POWER SUPPLY
4
1
V, min
V, max
VDD = 5 V 5%, ISOURCE = 10 mA
VDD = 5 V 5%, ISINK = 10 mA
For specified performance
5 V − 5%
VDD
4.75
5.25
3
V, min
V, max
mA, max
5 V + 5%
VDD
1 See plots in the Typical Performance Characteristics section.
2 See the Terminology section for explanation of specifications.
3 See the Fault Detection section for explanation of fault detection functionality.
4 See the Missing Neutral Detection section for explanation of missing neutral detection functionality.
5 Sample tested during initial release and after any redesign or process change that might affect this parameter.
TIMING CHARACTERISTICS
VDD = 5 V 5%, AGND = DGND = 0 V, on-chip reference, on-chip oscillator, TMIN to TMAX = −40°C to +85°C. Sample tested during
initial release and after any redesign or process change that might affect this parameter. See Figure 2.
Table 2.
Parameter
Value
Unit
Test Conditions/Comments
1
t1
120
See Table 7
1/2 t2
ms
s
s
ms
s
s
F1 and F2 Pulse Width (Logic High).
t2
t3
t4
Output Pulse Period. See the Transfer Function section.
Time Between F1 Falling Edge and F2 Falling Edge.
CF Pulse Width (Logic High).
CF Pulse Period. See the Transfer Function section.
Minimum Time Between F1 and F2 Pulse.
1
90
t5
t6
See Table 8
CLKIN/4
1 The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Transfer Function section.
t1
F1
t6
t2
t3
F2
t4
t5
CF
Figure 2. Timing Diagram for Frequency Outputs
Rev. 0 | Page 4 of 24
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