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AD9959BCPZ1 参数 Datasheet PDF下载

AD9959BCPZ1图片预览
型号: AD9959BCPZ1
PDF下载: 下载PDF文件 查看货源
内容描述: 4通道, 500 MSPS DDS ,10位DAC [4-Channel, 500 MSPS DDS with 10-Bit DACs]
分类和应用: 数据分配系统
文件页数/大小: 44 页 / 721 K
品牌: ADI [ ADI ]
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AD9959  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
Residual Phase Noise @ 100.3 MHz (fOUT  
)
with REFCLK Multiplier Enabled 5×  
@ 1 kHz Offset  
@ 10 kHz Offset  
@ 100 kHz Offset  
@ 1 MHz Offset  
−120  
−130  
−135  
−129  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Residual Phase Noise @ 15.1 MHz (fOUT  
)
with REFCLK Multiplier Enabled 20×  
@ 1 kHz Offset  
@ 10 kHz Offset  
@ 100 kHz Offset  
@ 1 MHz Offset  
−127  
−136  
−139  
−138  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Residual Phase Noise @ 40.1 MHz (fOUT  
)
with REFCLK Multiplier Enabled 20×  
@ 1 kHz Offset  
@ 10 kHz Offset  
@ 100 kHz Offset  
@ 1 MHz Offset  
−117  
−128  
−132  
−130  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Residual Phase Noise @ 75.1 MHz (fOUT  
)
with REFCLK Multiplier Enabled 20×  
@ 1 kHz Offset  
@ 10 kHz Offset  
@ 100 kHz Offset  
@ 1 MHz Offset  
−110  
−121  
−125  
−123  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Residual Phase Noise @ 100.3 MHz (fOUT  
)
with REFCLK Multiplier Enabled 20×  
@ 1 kHz Offset  
@ 10 kHz Offset  
@ 100 kHz Offset  
−107  
−119  
−121  
−119  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
@ 1 MHz Offset  
SERIAL PORT TIMING CHARACTERISTICS  
Maximum Frequency Serial Clock (SCLK)  
Minimum SCLK Pulse Width Low (tPWL  
Minimum SCLK Pulse Width High (tPWH  
200  
MHz  
ns  
ns  
ns  
ns  
)
1.6  
2.2  
2.2  
0
)
Minimum Data Setup Time (tDS  
Minimum Data Hold Time  
)
CS  
1.0  
12  
ns  
Minimum  
Setup Time (tPRE)  
Minimum Data Valid Time for Read Operation  
MISCELLANEOUS TIMING CHARACTERISTICS  
MASTER_RESET Minimum Pulse Width  
ns  
1
Min pulse width = 1 sync clock period  
Min pulse width = 1 sync clock period  
Rising edge to rising edge  
I/O_UPDATE Minimum Pulse Width  
1
4.8  
0
5.4  
0
2.5  
0
Minimum Setup Time (I/O_UPDATE to SYNC_CLK)  
Minimum Hold Time (I/O_UPDATE to SYNC_CLK)  
Minimum Setup Time (Profile Inputs to SYNC_CLK)  
Minimum Hold Time (Profile Inputs to SYNC_CLK)  
Minimum Setup Time (SDIO Inputs to SYNC_CLK)  
Minimum Hold Time (SDIO Inputs to SYNC_CLK)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Rising edge to rising edge  
Propagation Time Between REF_CLK and SYNC_CLK 2.25  
Profile Pin Toggle Rate  
3.5  
5.5  
2
Sync  
clocks  
CMOS LOGIC INPUTS  
VIH  
2.0  
V
VIL  
0.8  
12  
V
Logic 1 Current  
Logic 0 Current  
Input Capacitance  
3
−12  
2
μA  
μA  
pF  
Rev. B | Page 6 of 44