AD9959
GENERAL DESCRIPTION
The AD9959 consists of four direct digital synthesizer (DDS)
cores that provide independent frequency, phase, and amplitude
control on each channel. This flexibility can be used to correct
imbalances between signals due to analog processing, such as
filtering, amplification, or PCB layout-related mismatches.
Because all channels share a common system clock, they are
inherently synchronized. Synchronization of multiple devices
is supported.
The AD9959 can perform up to a 16-level modulation of fre-
quency, phase, or amplitude (FSK, PSK, ASK). Modulation is
performed by applying data to the profile pins. In addition, the
AD9959 also supports linear sweep of frequency, phase, or
amplitude for applications such as radar and instrumentation.
The AD9959 serial I/O port offers multiple configurations to
provide significant flexibility. The serial I/O port offers an SPI-
compatible mode of operation that is virtually identical to the
SPI operation found in earlier Analog Devices, Inc., DDS products.
Flexibility is provided by four data pins (SDIO_0/SDIO_1/
SDIO_2/SDIO_3) that allow four programmable modes of
serial I/O operation.
The AD9959 uses advanced DDS technology that provides low
power dissipation with high performance. The device incorporates
four integrated, high speed 10-bit DACs with excellent wideband
and narrow-band SFDR. Each channel has a dedicated 32-bit
AD9959
32
Σ
32
Σ
Σ
frequency tuning word, 14 bits of phase offset, and a 10-bit
output scale multiplier.
The DAC outputs are supply referenced and must be terminated
into AVDD by a resistor or an AVDD center-tapped transformer.
Each DAC has its own programmable reference to enable
different full-scale currents for each channel.
The DDS acts as a high resolution frequency divider with the
REFCLK as the input and the DAC providing the output. The
REFCLK input source is common to all channels and can be
driven directly or used in combination with an integrated
REFCLK multiplier (PLL) up to a maximum of 500 MSPS.
The PLL multiplication factor is programmable from 4 to 20,
in integer steps. The REFCLK input also features an oscillator
circuit to support an external crystal as the REFCLK source.
The crystal must be between 20 MHz and 30 MHz. The crystal
can be used in combination with the REFCLK multiplier.
The AD9959 comes in a space-saving 56-lead LFCSP package.
The DDS core (AVDD and DVDD pins) is powered by a 1.8 V
supply. The digital I/O interface (SPI) operates at 3.3 V and
requires DVDD_I/O (Pin 49) be connected to 3.3 V.
The AD9959 operates over the industrial temperature range of
−40°C to +85°C.
DDS CORE
15
cos(x)
10
10
DAC
CH0_IOUT
CH0_IOUT
DDS CORE
32
Σ
32
Σ
Σ
15
cos(x)
10
10
DAC
CH1_IOUT
CH1_IOUT
DDS CORE
32
Σ
32
Σ
Σ
15
cos(x)
10
10
DAC
CH2_IOUT
CH2_IOUT
DDS CORE
32
Σ
32
Σ
Σ
15
cos(x)
10
10
DAC
SCALABLE
DAC REF
CURRENT
CH3_IOUT
CH3_IOUT
DFTW
SYNC_IN
SYNC_OUT
I/O_UPDATE
SYNC_CLK
REF_CLK
REF_CLK
÷4
FTW
32
PHASE/
ΔPHASE
14
AMP/
ΔAMP
10
DAC_RSET
TIMING AND CONTROL LOGIC
SYSTEM
CLK
PWR_DWN_CTL
MASTER_RESET
CONTROL
REGISTERS
SCLK
CS
SDIO_0
SDIO_1
SDIO_2
SDIO_3
05246-001
REF CLOCK
MULTIPLIER
BUFFER/ 4× TO 20×
XTAL
OSCILLATOR
MUX
CHANNEL
REGISTERS
PROFILE
REGISTERS
1.8V
1.8V
DVDD
P0 P1
P2
P3
SERIAL
I/O
PORT
BUFFER
CLK_MODE_SEL
AVDD
DVDD_I/O
Figure 2. Detailed Block Diagram
Rev. B | Page 3 of 44
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