AD9959
SPECIFICATIONS
AVDD and DVDD = 1.8 V ± 5%; DVDD_I/O = 3.3 V ± 5%; T = 25°C; R
SET
= 1.91 kΩ; external reference clock frequency = 500 MSPS
(REFCLK multiplier bypassed), unless otherwise noted.
Table 1.
Parameter
REFERENCE CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Bypassed
REFCLK Multiplier Enabled
Internal VCO Output Frequency Range
VCO Gain Control Bit Set High
VCO Gain Control Bit Set Low
Crystal REFCLK Source Range
Input Level
Input Voltage Bias Level
Input Capacitance
Input Impedance
Duty Cycle with REFCLK Multiplier Bypassed
Duty Cycle with REFCLK Multiplier Enabled
CLK Mode Select (Pin 24) Logic 1 Voltage
CLK Mode Select (Pin 24) Logic 0 Voltage
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Channel-to-Channel Output Amplitude Matching Error
Output Current Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Voltage Compliance Range
Channel-to-Channel Isolation
WIDEBAND SFDR
1 MHz to 20 MHz Analog Output
20 MHz to 60 MHz Analog Output
60 MHz to 100 MHz Analog Output
100 MHz to 150 MHz Analog Output
150 MHz to 200 MHz Analog Output
NARROW-BAND SFDR
1.1 MHz Analog Output (±10 kHz)
1.1 MHz Analog Output (±50 kHz)
1.1 MHz Analog Output (±250 kHz)
1.1 MHz Analog Output (±1 MHz)
15.1 MHz Analog Output (±10 kHz)
15.1 MHz Analog Output (±50 kHz)
15.1 MHz Analog Output (±250 kHz)
15.1 MHz Analog Output (±1 MHz)
40.1 MHz Analog Output (±10 kHz)
40.1 MHz Analog Output (±50 kHz)
40.1 MHz Analog Output (±250 kHz)
40.1 MHz Analog Output (±1 MHz)
75.1 MHz Analog Output (±10 kHz)
Min
Typ
Max
Unit
Test Conditions/Comments
See Figure 34 and Figure 35
1
10
255
100
20
200
1.15
2
1500
45
35
1.25
500
125
500
160
30
1000
MHz
MHz
MHz
MHz
MHz
mV
V
pF
Ω
%
%
V
V
Bits
mA
%FS
%
μA
LSB
LSB
pF
V
dB
Measured at each pin (single-ended)
55
65
1.8
0.5
10
10
+10
+2.5
25
1.8 V digital input logic
1.8 V digital input logic
Must be referenced to AVDD
1.25
−
10
−2.5
1
±0.5
±1.0
3
AVDD − 0.50
65
AVDD + 0.50
DAC supplies tied together
(see Figure 19)
The frequency range for wideband
SFDR is defined as dc to Nyquist
−
65
−
62
−
59
−
56
−
53
−
90
−
88
−
86
−
85
−
90
−
87
−
85
−
83
−
90
−
87
−
84
−82
−87
Rev. B | Page 4 of 44
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
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