AD9883A
Table XXX. Vsync Detection Results
13
14
7–0 Post-Coast
This register allows the coast signal to be applied follow-
ing the Vsync signal. This is necessary in cases where
post-equalization pulses are present. The step size for this
control is one Hsync period.
Detect
Function
0
1
No Activity Detected
Activity Detected
The default is 0.
The Sync Processing Block Diagram (Figure 12) shows
where this function is implemented.
7
Hsync Detect
This bit is used to indicate when activity is detected on
the Hsync input pin (Pin 30). If Hsync is held high or
low, activity will not be detected.
14
3 AVS – Active Vsync
This bit indicates which Vsync source is being used: the
Vsync input or output from the sync separator. Bit 4 in this
register determines which is active. If both Vsync and
SOG are detected, the user can determine which has
priority via Bit 0 in register 0EH. The user can override this
function via Bit 1 in register 0EH. If the override bit is set
to Logic 1, this bit will be forced to whatever the state of Bit 0
in register 0EH is set.
Table XXVII. Hsync Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
The sync processing block diagram shows where this
function is implemented.
Table XXXI. Active Vsync Results
Bit 4, Reg 14H
(Vsync Detect)
Bit 1, Reg 0EH
(Override)
14
6 AHS – Active Hsync
AVS
This bit indicates which Hsync input source is being used
by the PLL (Hsync input or Sync-on-Green). Bits 7 and 1
in this register determine which source is used. If both
Hsync and SOG are detected, the user can determine which
has priority via Bit 3 in register 0EH. The user can override
this function via Bit 4 in register 0EH. If the override bit
is set to Logic 1, then this bit will be forced to whatever
the state of Bit 3 in register 0EH is set to.
1
0
X
0
0
1
0
1
Bit 0 in 0EH
AVS = 0 means Vsync input.
AVS = 1 means Sync separator.
The override bit is in register 0EH, Bit 1.
14
2
Detected Vsync Output Polarity Status
Table XXVIII. Active Hsync Results
This bit reports the status of the Vsync output polarity
detection circuit. It can be used to determine the polarity
of the Vsync output. The detection circuit’s location is-
shown in the Sync Processing Block Diagram (Figure 12).
Bit 7
Bit 1
(SOG
Detect) Detect)
Bit 4,
Reg 0EH
(Override)
(Hsync
AHS
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
Bit 3 in 0EH
1
0
Bit 3 in 0EH
Bit 3 in 0EH
Table XXXII. Detected Vsync Output Polarity Status
Vsync Polarity Status Result
0
1
Active Low
Active High
AHS = 0 means use the Hsync pin input for Hsync.
AHS = 1 means use the SOG pin input for Hsync.
14
1
Sync-on-Green Detect
This bit is used to indicate when sync activity is detected
on the Sync-on-Green input pin (Pin 49).
The override bit is in register 0EH, Bit 4.
14
5 Detected Hsync Input Polarity Status
Table XXXIII. Sync-on-Green Detection Results
This bit reports the status of the Hsync input polarity
detection circuit. It can be used to determine the polarity
of the Hsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 12).
Detect
Function
0
1
No Activity Detected
Activity Detected
Table XXIX. Detected Hsync Input Polarity Status
Hsync Polarity Status Result
The Sync Processing Block Diagram (Figure 12) shows
where this function is implemented.
0
1
Negative
Positive
14
0
Detected Coast Polarity Status
This bit reports the status of the Coast input polarity
detection circuit. It can be used to determine the polarity
of the Coast input. The detection circuit’s location is shown
in the Sync Processing Block Diagram (Figure 12).
14
4
Vsync Detect
This bit is used to indicate when activity is detected on
the Vsync input pin (Pin 31). If Vsync is held steady high
or low, activity will not be detected.
REV. B
–21–
ADI [ ADI ]
