AD9883A
0E
0E
0E
5
Hsync Output Polarity
0E
0 Active Vsync Select
This bit is used to select the active Vsync when the over-
ride bit is set (Bit 1).
This bit determines the polarity of the Hsync output and
the SOG output. Table XI shows the effect of this option.
SYNC indicates the logic state of the sync pulse.
Table XVI. Active Vsync Select Settings
Table XI. Hsync Output Polarity Settings
Select
Result
Setting
SYNC
0
1
Vsync Input
Sync Separator Output
0
1
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
The default for this register is 0.
7 Clamp Input Signal Source
This bit determines the source of clamp timing.
The default setting for this register is 0.
Active Hsync Override
0F
4
This bit is used to override the automatic Hsync selection,
To override, set this bit to Logic 1. When overriding, the
active Hsync is set via Bit 3 in this register.
Table XVII. Clamp Input Signal Source Settings
Clamp Function
Function
Table XII. Active Hsync Override Settings
Override Result
0
1
Internally Generated Clamp Signal
Externally Provided Clamp Signal
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the leading edge of Hsync.
0
1
Autodetermines the Active Interface
Override, Bit 3 Determines the Active Interface
The default for this register is 0.
Active Hsync Select
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is active.
The polarity of CLAMP is determined by the Clamp
Polarity bit (Register 0FH, Bit 6).
3
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 4). Alter-
nately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
The power-up default value is Clamp Function = 0.
0F
6 Clamp Input Signal Polarity
This bit determines the polarity of the externally provided
CLAMP signal.
Table XIII. Active HSYNC Select Settings
Select
Result
Table XVIII. Clamp Input Signal Polarity Settings
0
1
HSYNC Input
Sync-on-Green Input
Clamp Function
Function
1
0
Active Low
Active High
The default for this register is 0.
Vsync Output Invert
0E
2
This bit inverts the polarity of the Vsync output. Table
XIV shows the effect of this option.
A Logic 1 means that the circuit will clamp when CLAMP is
low, and it will pass the signal to the ADC when CLAMP is
high.
Table XIV. Vsync Output Invert Settings
A Logic 0 means that the circuit will clamp when CLAMP
is high, and it will pass the signal to the ADC when
CLAMP is low.
Setting
Vsync Output
0
1
Invert
No Invert
The power-up default value is Clamp Polarity = 1.
0F
5 Coast Select
The default setting for this register is 0.
Active Vsync Override
This bit is used to override the automatic Vsync selection.
To override, set this bit to Logic 1. When overriding, the
active interface is set via Bit 0 in this register.
This bit is used to select the active Coast source. The
choices are the Coast Input Pin or Vsync. If Vsync is se-
lected the additional decision of using the Vsync input
pin or the output from the sync separator needs to be
made (Register 0E, Bits 1, 0).
0E
1
Table XIX. Power-Down Settings
Table XV. Active Vsync Override Settings
Select
Result
Override
Result
0
1
Coast Input Pin
Vsync (See above Text)
0
1
Autodetermine the Active Vsync
Override, Bit 0 Determines the Active Vsync
The default for this register is 0.
REV. B
–19–
ADI [ ADI ]
