AD9883A
0F
4 Coast Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the Coast signal going into the PLL.
The default setting is 23, which corresponds to a threshold
value of 100 mV; for a threshold of 150 mV, the setting
should be 18.
10
2 Red Clamp Select
Table XX. Coast Input Polarity Override Settings
This bit determines whether the Red channel is clamped to
ground or to midscale. For RGB video, all three chan-
nels are referenced to ground. For YCbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 37.
Override Bit
Result
0
1
Determined by Chip
Determined by User
The default for coast polarity override is 0.
3 Coast Input Polarity
0F
Table XXIV. Red Clamp Select Settings
This bit indicates the polarity of the Coast signal that is
applied to the PLL COAST input.
Clamp
Function
0
1
Clamp to Ground
Clamp to Midscale (Pin 37)
Table XXI. Coast Input Polarity Settings
Coast Polarity
Function
The default setting for this register is 0.
1 Green Clamp Select
This bit determines whether the Green channel is clamped
to ground or to midscale.
0
1
Active Low
Active High
10
10
11
Active Low means that the clock generator will ignore
Hsync inputs when Coast is low, and continue operating at
the same nominal frequency until Coast goes high.
Table XXV. Green Clamp Select Settings
Clamp
Function
Active High means that the clock generator will ignore
Hsync inputs when Coast is high, and continue operating at
the same nominal frequency until Coast goes low.
0
1
Clamp to Ground
Clamp to Midscale (Pin 37)
This function needs to be used along with the Coast
Polarity Override bit (Bit 4).
The default setting for this register is 0.
Blue Clamp Select
0
The power-up default value is 1.
This bit determines whether the Blue channel is clamped
to ground or to midscale.
0F
0F
10
2 Seek Mode Override
This bit is used to either allow or disallow the low power
mode. The low power mode (Seek Mode) occurs when
there are no signals on any of the Sync inputs.
Table XXVI. Blue Clamp Select Settings
Clamp
Function
Table XXII. Seek Mode Override Settings
0
1
Clamp to Ground
Clamp to Midscale (Pin 37)
Select
Result
1
0
Allow Seek Mode
Disallow Seek Mode
The default setting for this register is 0.
7–0 Sync Separator Threshold
This register is used to set the responsiveness of the sync
separator. It sets how many internal 5 MHz clock periods
the sync separator must count to before toggling high or
low. It works like a low-pass filter to ignore Hsync pulses
in order to extract the Vsync signal. This register should
be set to some number greater than the maximum Hsync
pulsewidth. Note that the sync separator threshold uses an
internal dedicated clock with a frequency of approxi-
mately 5 MHz.
The default for this register is 1.
PWRDN
This bit is used to put the chip in full power-down. See
Power Management Section for details of which blocks
are powered down.
1
Table XXIII. Power-Down Settings
Select
Result
The default for this register is 32.
0
1
Power-Down
Normal Operation
12
7–0 Pre-Coast
This register allows the coast signal to be applied prior to
the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. The step size for this
control is one Hsync period.
The default for this register is 1.
7-3 Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the Sync-
on-Green slicer to be adjusted. This register adjusts it in
steps of 10 mV, with the minimum setting equaling 10 mV
(11111) and the maximum setting equaling 330 mV (00000).
The default is 0.
–20–
REV. B
ADI [ ADI ]
