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AD9865BCPZRL 参数 Datasheet PDF下载

AD9865BCPZRL图片预览
型号: AD9865BCPZRL
PDF下载: 下载PDF文件 查看货源
内容描述: 宽带调制解调器混合信号前端 [Broadband Modem Mixed-Signal Front End]
分类和应用: 调制解调器电信集成电路电信电路
文件页数/大小: 48 页 / 2209 K
品牌: AD [ ANALOG DEVICES ]
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AD9865
Parameter
POWER CONSUMPTION (Half-Duplex Operation with f
DATA
= 50 MSPS)
Tx Mode
I
AVDD
+ I
CLKVDD
I
DVDD
+ I
DRVDD
Rx Mode
I
AVDD
+ I
CLKVDD
I
DVDD
+ I
DRVDD
POWER CONSUMPTION OF FUNCTIONAL BLOCKS
(I
AVDD
+ I
CLKVDD
)
RxPGA and LPF
ADC
TxDAC
IAMP (Programmable)
Reference
CLK PLL and Synthesizer
MAXIMUM ALLOWABLE POWER DISSIPATION
STANDBY POWER CONSUMPTION
IS_TOTAL (Total Supply Current)
POWER DOWN DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and synthesizer
POWER UP DELAY (USING PWR_DWN PIN)
RxPGA and LPF
ADC
TxDAC
IAMP
CLK PLL and Synthesizer
Temp
Test Level
Min
Typ
Max
Unit
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
IV
IV
IV
IV
III
III
III
III
III
III
IV
112
46
225
36.5
87
108
38
10
170
107
130
49.5
253
39
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
mA
ns
ns
ns
ns
ns
µs
ns
µs
ns
µs
120
1.66
13
III
III
III
III
III
III
III
III
III
III
440
12
20
20
27
7.8
88
13
20
20
1
2
Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent.
Default power-up settings for MODE = LOW and CONFIG = LOW.
DIGITAL SPECIFICATIONS
AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; R
SET
= 2 kΩ, unless otherwise noted.
Table 4.
Parameter
CMOS LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
Input Leakage Current
Input Capacitance
CMOS LOGIC OUTPUTS (C
LOAD
= 5 pF)
High Level Output Voltage (I
OH
= 1 mA)
Low Level Output Voltage (I
OH
= 1 mA)
Output Rise/Fall Time (High Strength Mode and C
LOAD
= 15 pF)
Output Rise/Fall Time (Low Strength Mode and C
LOAD
= 15 pF)
Output Rise/Fall Time (High Strength Mode and C
LOAD
= 5 pF)
Output Rise/Fall Time (Low Strength Mode and C
LOAD
= 5 pF)
RESET
Minimum Low Pulse Width (Relative to f
ADC
)
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test Level
VI
VI
VI
VI
VI
VI
VI
VI
VI
DRVDD – 0.7
0.4
1.5/2.3
1.9/2.7
0.7/0.7
1.0/1.0
1
Min
DRVDD – 0.7
0.4
12
3
Typ
Max
Unit
V
V
µA
pF
V
V
ns
ns
ns
ns
Clock
cycles
Rev. A | Page 6 of 48