AD9865
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
58
63 62 61 60 59
57 56 55 54 53
51 50 49
52
48 AVSS
1
2
3
4
5
6
ADIO9/Tx[5]
ADIO8/Tx[4]
ADIO7/Tx[3]
ADIO6/Tx[2]
ADIO5/Tx[1]
ADIO4/Tx[0]
ADIO3/Rx[5]
ADIO2/Rx[4]
ADIO1/Rx[3]
ADIO0/Rx[2]
NC/Rx[1]
47 AVSS
PIN 1
IDENTIFIER
46 IOUT_N–
45
IOUT_G–
44
AVSS
43
AVDD
REFIO
REFADJ
AVDD
AVSS
RX+
AD9865
42
41
40
39
38
7
8
TOP VIEW
(Not to Scale)
9
10
11
37
RX–
12
13
NC/Rx[0]
36 AVSS
RXEN/RXSYNC
35
34
AVDD
AVSS
TXEN/TXSYNC 14
15
16
TXCLK/TXQUIET
RXCLK
33 REFT
17 18 19 20 21 22 23 24 25 26 27 28
30 31 32
29
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
ADIO9
Tx[5]
Mode1
HD
FD
Description
MSB of ADIO Buffer
1
MSB of Tx Nibble Input
Bits 8 to 5 of ADIO Buffer
Bits 4 to 1 of Tx Nibble Input
Bit 4 of ADIO Buffer
LSB of Tx Nibble Input
Bit 3 of ADIO Buffer
MSB of Rx Nibble Output
Bits 2 to 1 of ADIO Buffer
Bits 4 to 3 of Rx Nibble Output
LSB of ADIO Buffer
Bit 2 of Rx Nibble Output
No Connect
Bit 1 of Rx Nibble Output
No Connect
LSB of Rx Nibble Output
ADIO Buffer Control Input
Rx Data Synchronization Output
Tx Path Enable Input
Tx Data Synchronization Input
2 to 5
6
ADIO8 to 5
Tx[4 to 1]
ADIO4
Tx[0]
HD
FD
HD
FD
7
ADIO3
Rx[5]
HD
FD
8, 9
10
11
12
13
14
ADIO2, 1
Rx[4, 3]
ADIO0
Rx[2]
HD
FD
HD
FD
NC
Rx[1]
HD
FD
NC
Rx[0]
HD
FD
RXEN
RXSYNC
TXEN
HD
FD
HD
FD
TXSYNC
Rev. A | Page 10 of 48
ADI [ ADI ]
