AD9865
Pin No.
Mnemonic
TXCLK
TXQUIET
Mode1
HD
Description
15
ADIO Sample Clock Input
Fast TxDAC/IAMP Power-Down
FD
16
RXCLK
HD
FD
ADIO Request Clock Input
Rx and Tx Clock Output at 2 x fADC
Digital Output Driver Supply Input
Digital Output Driver Supply Return
fADC/N Clock Output (L = 1, 2, 4, or 8)
Serial Port Data Input/Output
Serial Port Data Output
17, 64
18, 63
19
DRVDD
DRVSS
CLKOUT1
SDIO
20
21
SDO
22
SCLK
Serial Port Clock Input
23
SEN
Serial Port Enable Input
24
GAIN
FD
HD or FD
HD or FD
Tx Data Port (Tx[5:0]) Mode Select
MSB of PGA Input Data Port
Bits 4 to 0 of PGA Input Data Port
Reset Input (Active Low)
PGA[5]
PGA[4 to 0]
RESET
25 to 29
30
31, 34, 36, 39, 44, 47, 48
AVSS
Analog Ground
32, 33
35, 40, 43
37, 38
41
REFB, REFT
AVDD
ADC Reference Decoupling Nodes
Analog Power Supply Input
RX−, RX+
REFADJ
REFIO
Receive Path − and + Analog Inputs
TxDAC Full-Scale Current Adjust
TxDAC Reference Input/Output
−Tx Amp Current Output_Sink
−Tx Mirror Current Output_Sink
+Tx Amp Current Output_Sink
+Tx Mirror Current Output_Sink
−TxDAC Current Output_Source
+TxDAC Current Output_Source
42
45
IOUT_G−
IOUT_N−
IOUT_G+
IOUT_N+
IOUT_P−
IOUT_P+
MODE
46
49
50
51
52
53
Digital Interface Mode Select Input
LOW = HD, HIGH = FD
54
55
56
57
58
59
60
61
62
CONFIG
CLKVSS
XTAL
Power-Up SPI Register Default Setting Input
Clock Oscillator/Synthesizer Supply Return
Crystal Oscillator Inverter Output
Crystal Oscillator Inverter Input
Clock Oscillator/Synthesizer Supply
Digital Supply Return
OSCIN
CLKVDD
DVSS
DVDD
Digital Supply Input
CLKOUT2
PWR_DWN
fOSCIN/L Clock Output, (L = 1, 2, or 4)
Power-Down Input
1 HD = half-duplex mode; FD = full-duplex mode.
Rev. A | Page 11 of 48
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