AD9865
1:1
Table 19. SPI Registers for TxDAC and IAMP
Address (Hex)
Bit
(0)
(7)
Description
R
R
L
S
0.1µF
R
SET
0x0E
TxDAC output
0x10
Enable current mirror gain settings
IOUTN+
(6:4) Secondary path first stage gain of 0
to 4 with ∆ = 1
IOUTG+
(3)
Not used
IAMP
TxDAC
(2:0) Primary path NMOS gain of 0 to 4
with ∆ = 1
0 TO –7.5dB
0 TO –12dB
IOUTN–
IOUTG–
0x11
0x12
(7)
Don’t care
(6:4) Secondary path second stage gain of
0 to 1.5 with ∆ = 0.25
(3)
Not used
Figure 63. TxDAC Output Directly via Center-Tap Transformer
(2:0) Secondary path third stage gain of 0
to 5 with ∆ = 1
The TxDAC is capable of delivering up to 10 dBm peak power
to a load, RL. To increase the peak power for a fixed standing
current, one must increase V p-p across IOUTP+ and IOUTP−
by increasing one or more of the following parameters: RS, RL (if
possible), and/or the turns ratio, N, of transformer. For exam-
ple, the removal of RS and the use of a 2:1 impedance ratio
transformer in the previous example results in 10 dBm of peak
power capabilities to the load. Note that increasing the power
output capabilities of the TxDAC reduces the distortion per-
formance due to the higher voltage swings seen at IOUTP+ and
IOUTP−. See Figure 27 through Figure 38 for performance
plots on the TxDAC’s ac performance. Optimum distortion
performance can typically be achieved by:
(6:4) IOFF2, secondary path standing
current
(2:0) IOFF1, primary path standing current
Tx PROGRAMMABLE GAIN CONTROL
TxPGA functionality is also available to set the peak output
current from the TxDAC or IAMP. The TxDAC and IAMP are
digitally programmable via the PGA[5:0] port or SPI over a 0 dB
to −7.5 dB and 0 dB to −19.5 dB range, respectively, in 0.5 dB
increments.
The TxPGA can be considered as two cascaded attenuators with
the TxDAC providing 7.5 dB range in 0.5 dB increments, and
the IAMP providing 12 dB range in 6 dB increments. As a
result, the IAMP’s composite 19.5 dB span is valid only if
Register 0x10 remains at its default setting of 0x44. Modifying
this register setting corrupts the LUT and results in an invalid
gain mapping.
•
Limiting the peak positive VIOUTP+ and VIOUTP− to 0.8 V to
avoid onset of TxDAC’s output compression. (TxDAC’s
voltage compliance is around 1.2 V.)
•
Limiting V p-p seen at IOUTP+ and IOUTP− to less
than 1.6 V.
Applications demanding higher output voltage swings and
power drive capabilities can benefit from using the IAMP.
TxDAC OUTPUT OPERATION
The differential current output of the TxDAC is available at the
IOUTP+ and IOUTP− pins and the IAMP should be disabled
by setting Bit 0 of Register 0x0E. Any load connected to these
pins must be ground referenced to provide a dc path for the
current sources. Figure 63 shows the outputs of the TxDAC
driving a doubly terminated 1:1 transformer with its center-tap
tied to ground. The peak-to-peak voltage, V p-p, across RL (and
IOUT+ to IOUT−) is equal to 2 × I × (RL//RS). With I = 10 mA
and RL = RS = 50 Ω, V p-p is equal to 0.5 V with 1 dBm of peak
power being delivered to RL and 1 dBm being dissipated in RS.
IAMP CURRENT-MODE OPERATION
The IAMP can be configured for the current-mode operation as
shown in Figure 64 for loads remaining relatively constant. In
this mode, the primary path mirrors should be used to deliver
the signal-dependent current to the load via a center-tapped
transformer, because it provides the best linearity performance.
Because the mirrors exhibit a high output impedance, they can
be easily back-terminated (if required).
For peak signal currents (IOUTPK up to 50 mA), only the
primary path mirror gain should be used for optimum
distortion performance and power efficiency. The primary
path’s gain should be set to 4, with the secondary path’s gain
stages set to 0 (Register 0x10 = 0x84). The TxDAC’s standing
current, I, can be set between 2.5 mA and 12.5 mA with the
IOUTP outputs left open. The IOUTN outputs should be
connected to the transformer, with the IOUTG (and IOUTP)
Rev. A | Page 30 of 48
ADI [ ADI ]
