AD9865
48
42
36
30
24
18
12
6
tSU
RXCLK
tHD
Tx SYNC
Tx [5:0]
GAIN
GAIN
Figure 57. Updating RxPGA via Tx[5:0] in Full-Duplex Mode
0
Updating the RxPGA (or TxPGA) via the PGA[5:0] port is an
option for both the half-duplex3 and full-duplex interface. The
PGA port consists of an input buffer that passes the 6-bit data
appearing at its input directly to the RxPGA (or TxPGA) gain
register with no gating signal required. Bit 5 or Bit 6 of
Register 0x0B is used to select whether the data updates the
RxPGA or TxPGA gain register. In applications that switch
between RxPGA and TxPGA gain control via PGA[5:0], be
careful that the RxPGA (or TxPGA) is not inadvertently loaded
with the wrong data during a transition. In the case of an
RxPGA to TxPGA transition, first deselect the RxPGA gain
register, update the PGA[5:0] port with the desired TxPGA gain
setting, and then select the TxPGA gain register.
–6
–12
0
6
12
18
24
30
36
42
48
54
60
66
6-BIT DIGITAL WORD-DECIMAL EQUIVALENT
Figure 56. Digital Gain Mapping of RxPGA
Table 15. SPI Registers RxPGA Control
Address
(Hex)
Bit
Description
0x09
(6)
Enable RxPGA update via SPI
(5:0) RxPGA gain code
0x0B
(6)
(5)
(3)
(2)
(1)
Select TxPGA via PGA[5:0]
Select RxPGA via PGA[5:0]
Enable software GAIN strobe – Full-duplex
Enable RxPGA update via Tx[5:0] – Full-duplex
3-bit RxPGA gain mapping – Half-duplex
The RxPGA also offers an alternative 3-bit word gain mapping
option4 that provides a −12 dB to +36 dB span in 8 dB increments
as shown in Table 16. The 3-bit word is directed to PGA[5:3]
with PGA[5] being the MSB. This feature is backward-compatible
with the AD9975 MxFE and allows direct interfacing to the
CX11647 or INT5130 HomePlug 1.0 PHYs.
The RxPGA gain register can be updated via the Tx[5:0] port,
the PGA[5:0] port, or the SPI port. The first two methods allow
fast updates of the RxPGA gain register and should be
Table 16. PGA Timing for AD9975 Backward-Compatible
Mode
considered for digital AGC functions requiring a fast closed-
loop response. The SPI port allows direct update and readback
of the RxPGA gain register via Register 0x09 with an update
rate limited to 1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6
of Register 0x09 must be set for a read or write operation.
Digital Gain Setting
PGA[5:3]
000
001
010
011
100
101
110
111
Decimal
Gain (dB)
0
1
2
3
4
5
6
7
−12
−12
−4
4
12
20
28
36
Updating the RxPGA via the Tx[5:0] port is an option only in
full-duplex mode1. In this case, a high level on the GAIN pin,2
with TXSYNC low, programs the PGA setting on either the
rising edge or falling edge of RXCLK, as shown in Figure 57.
The GAIN pin must be held high, TXSYNC must be held low,
and GAIN data must be stable for one or more clock cycles to
update the RxPGA gain setting.
A low level on the GAIN pin enables data to be fed to the digital
interpolation filter. This interface should be considered when
upgrading existing designs from the AD9875/AD9876 MxFE
products or half-duplex applications trying to minimize an
ASIC’s pin count.
1 Default setting for full-duplex mode (MODE = 1).
2 The GAIN strobe can also be set in software via Reg. 0x0B, Bit 3 for
continuous updating. This eliminates the requirement for external GAIN
signal, reducing the ASIC pin count by 1.
3 Default setting for half-duplex mode (MODE = 0).
4 Default setting for MODE = 0 and CONFIG =1.
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