AD9865
TRANSMIT PATH
The AD9865 (or AD9866) transmit path consists of a selectable
digital 2×/4× interpolation filter, a 10-bit or 12-bit TxDAC, and
a current-output amplifier (IAMP) as shown in Figure 59. Note
that the additional two bits of resolution offered by the AD9866
result in a 10 dB to 12 dB reduction in the pass-band noise
floor. The digital interpolation filter relaxes the Tx analog
filtering requirements by simultaneously reducing the images
from the DAC reconstruction process while increasing the
analog filter’s transition band. The digital interpolation filter
can also be bypassed, resulting in lower digital current
consumption.
The pipeline delays of the 2× and 4× filter responses are 21.5
and 24 clock cycles, respectively, relative to fDATA. The filter delay
is also taken into consideration for applications configured for a
half-duplex interface with the half-duplex power-down mode
enabled. This feature allows the user to set a programmable
delay that powers down the TxDAC and IAMP only after the
last Tx input sample has propagated through the digital filter.
See the Power Control and Dissipation section for more details.
2.5
10
0
WIDE BAND
2.0
1.5
–10
–20
–30
–40
–50
–60
–70
–80
–90
1.0
0.5
PASS BAND
IOUT_G+
0
ADIO[11:6]/
2-4X
IOUT_N+
IOUT_N–
IOUT_G–
10
TxDAC
IAMP
Tx[5:0]
–0.5
–1.0
–1.5
–2.0
–2.5
–1.0dB @ 0.441 fDATA
0 TO –12dB
0 TO –7.5dB
ADIO[11:6]/
Rx[5:0]
AD9865/AD9866
TXEN/SYNC
TXCLK
Figure 59. Functional Block Diagram of Tx Path
0
0.25
0.50
0.75
1.00
1.25
1.75
2.00
1.50
NORMALIZED FREQUENCY (Relative to fDATA
)
DIGITAL INTERPOLATION FILTERS
Figure 60. Frequency Response of 2× Interpolation Filter
(Normalized to fDATA
The input data from the Tx port can be fed into a selectable
2×/4× interpolation filter or directly into the TxDAC (for a half-
duplex only). The interpolation factor for the digital filter is set
via SPI Register 0x0C with the settings shown in Table 18. The
maximum input word rate, fDATA, into the interpolation filter is
80 MSPS% the maximum DAC update rate is 200 MSPS. There-
fore, applications with input word rates at or below 50 MSPS
can benefit from 4× interpolation, while applications with input
word rates between 50 MSPS and 80 MSPS can benefit from
2× interpolation.
)
2.5
10
0
WIDE BAND
2.0
1.5
–10
–20
–30
–40
–50
–60
–70
–80
–90
1.0
0.5
PASS BAND
0
–1.0dB @ 0.45 fDATA
–0.5
–1.0
–1.5
–2.0
–2.5
Table 18. Interpolation Factor Set via SPI Register 0x0C
Bits [7:6]
Interpolation Factor
00
01
10
11
4
2
0
0.5
1.0
1.5
2.0
2.5
3.5
4.0
3.0
NORMALIZED FREQUENCY (Relative to fDATA
)
1 (half-duplex only)
Do not use
Figure 61. Frequency Response of 4× Interpolation Filter
(Normalized to fDATA
)
The interpolation filter consists of two cascaded half-band filter
stages with each stage providing 2× interpolation. The first
stage filter consists of 43 taps. The second stage filter, operating
at the higher data rate, consists of 11 taps. The normalized
wideband and pass-band filter responses (relative fDATA) for the
2× and 4× low-pass interpolation filters are shown in Figure 60
and Figure 61, respectively. These responses also include the
inherent sinc(x) from the TxDAC reconstruction process and
can be used to estimate any post analog filtering requirements.
TxDAC AND IAMP ARCHITECTURE
The Tx path contains a TxDAC with a current amplifier, IAMP.
The TxDAC reconstructs the output of the interpolation filter
and sources a differential current output that can be directed to
an external load or fed into the IAMP for further amplification.
The TxDAC’s and IAMPS’s peak current outputs are digitally
programmable over a 0 to −7.5 dB and 0 to −19.5 dB range,
respectively, in 0.5 dB increments. Note that this assumes
default register settings for Register 0x10 and Register 0x11.
Rev. A | Page 28 of 48
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