AD9851
Parameter
TIMING CHARACTERISTICS
4
t
WH
, t
WL
(W_CLK Min Pulsewidth High/Low)
t
DS
, t
DH
(Data to W_CLK Setup and Hold Times)
t
FH
, t
FL
(FQ_UD Min Pulsewidth High/Low)
t
CD
(REFCLK Delay After FQ_UD)
5
t
FD
(FQ_UD Min Delay After W_CLK)
t
CF
(Output Latency from FQ_UD)
Frequency Change
Phase Change
t
RH
(CLKIN Delay After RESET Rising Edge)
t
RL
(RESET Falling Edge After CLKIN)
t
RR
(Recovery from RESET)
t
RS
(Minimum RESET Width)
t
OL
(RESET Output Latency)
Wake-Up Time from Power-Down Mode
6
CMOS LOGIC INPUTS
Logic “1” Voltage, +5 V Supply
Logic “1” Voltage, +3.3 V Supply
Logic “1” Voltage, +2.7 V Supply
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Rise/Fall Time
Input Capacitance
POWER SUPPLY
V
S6
Current @:
62.5 MHz Clock, +2.7 V Supply
100 MHz Clock, +2.7 V Supply
62.5 MHz Clock, +3.3 V Supply
125 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +5 V Supply
125 MHz Clock, +5 V Supply
180 MHz Clock, +5 V Supply
Power Dissipation @ :
62.5 MHz Clock, +5 V Supply
62.5 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +2.7 V Supply
100 MHz Clock, +2.7 V Supply
125 MHz Clock, +5 V Supply
125 MHz Clock, +3.3 V Supply
180 MHz Clock, +5 V Supply
P
DISS
Power-Down Mode @:
+5 V Supply
+2.7 V Supply
Temp
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
FULL
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Test
Level
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
I
I
I
I
I
I
IV
V
3.5
3.0
2.4
0.4
12
12
100
3
Min
3.5
3.5
7
3.5
7
18
13
3.5
3.5
2
5
13
5
AD9851BRS
Typ
Max
Units
ns
ns
ns
ns
ns
SYSCLK
Cycles
SYSCLK
Cycles
ns
ns
SYSCLK
Cycles
SYSCLK
Cycles
SYSCLK
Cycles
µs
V
V
V
V
µA
µA
ns
pF
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
30
40
35
55
50
70
110
250
115
85
110
365
180
555
17
4
35
50
45
70
65
90
130
325
150
95
135
450
230
650
55
20
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
mW
mW
mW
NOTES
1
+V
S
collectively refers to the positive voltages applied to DVDD, PVCC and AVDD. Voltages applied to these pins should be of the same potential.
2
Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. This specifies the p-p signal level and dc offset needed when
the clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0 V dc offset.
3
The comparator’s jitter contribution to any input signal. This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more
output jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic
signals (spur’s, noise), slower slew rate and low comparator overdrive.
4
Timing of input signals FQ_UD, WCLK, RESET are asynchronous to the Reference Clock; however, the presence of a Reference Clock is required to implement
those functions. In the absence of a Reference Clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable
until a Reference Clock is restored. Very high speed updates of frequency/phase word will require FQ_UD and WCLK to be externally synchronized with the exter-
nal Reference Clock to assure proper timing.
5
Not applicable when 6× REFCLK Multiplier is engaged.
6
Assumes no capacitive load on DACBP (Pin 17).
Specifications subject to change without notice.
REV. C
–3–
AD [ ANALOG DEVICES ]
