AD9850
+V
S
GND
IOUT
100k
8-b 5 PARALLEL DATA,
DATA OR 1-b 40 SERIAL DATA,
PROCESSOR BUS RESET, AND 2
CLOCK LINES
100k
AD9850
IOUTB
VINN
XTAL
CLK
VINP
OSC
QOUT
QOUTB
RSET
5-POLE ELLIPTICAL
42MHz LOW-PASS
200 IMPEDANCE
LOW-PASS
FILTER
200
470pF
IF
FREQUENCY
IN
FILTER
125MHz
FILTER
RF
FREQUENCY
OUT
AD9850
COMPLETE DDS
REFERENCE
TUNING
WORD
100
3a. Frequency/Phase–Agile Local Oscillator
RF
FREQUENCY
OUT
VCO
CMOS
CLOCK
OUTPUTS
COMP
200
125MHz
REFERENCE
CLOCK
AD9850
COMPLETE
DDS
FILTER
PHASE
COMPARATOR
DIVIDE-BY-N
LOOP
FILTER
TRUE
Figure 1. Basic AD9850 Clock Generator Application
with Low-Pass Filter
TUNING
WORD
3b. Frequency/Phase–Agile Reference for PLL
REF
FREQUENCY
PHASE
COMPARATOR
FILTER
LOOP
FILTER
VCO
Rx
IF IN
I/Q MIXER
AD9059
AND
LOW-PASS Q DUAL 8-BIT 8
ADC
FILTER
VCA
ADC CLOCK
FREQUENCY
LOCKED TO Tx CHIP/
SYMBOL PN RATE
125MHz
I
8
DIGITAL
DEMODULATOR
Rx
BASEBAND
DIGITAL
DATA
OUT
AGC
RF
FREQUENCY
OUT
PROGRAMMABLE
DIVIDE-BY-N
FUNCTION
ADC ENCODE
AD9850
COMPLETE
DDS
TUNING WORD
REFERENCE
CLOCK
32
CLOCK
GENERATOR CHIP/SYMBOL/PN
RATE DATA
AD9850
3c. Digitally-Programmable Divide-by-N Function in PLL
Figure 3. AD9850 Complete DDS Synthesizer in
Frequency Up-Conversion Applications
Figure 2. AD9850 Clock Generator Application in a
Spread-Spectrum Receiver
THEORY OF OPERATION AND APPLICATION
The AD9850 uses direct digital synthesis (DDS) technology, in the
form of a numerically controlled oscillator, to generate a frequency/
phase-agile sine wave. The digital sine wave is converted to analog
form via an internal 10-bit high speed D/A converter, and an
on-board high speed comparator is provided to translate the analog
sine wave into a low jitter TTL/CMOS compatible output square
wave. DDS technology is an innovative circuit architecture that
allows fast and precise manipulation of its output frequency under
full digital control. DDS also enables very high resolution in the
incremental selection of output frequency; the AD9850 allows an
output frequency resolution of 0.0291 Hz with a 125 MHz refer-
ence clock applied. The AD9850’s output waveform is phase con-
tinuous when changed.
The basic functional block diagram and signal flow of the
AD9850 configured as a clock generator is shown in Figure 4.
The DDS circuitry is basically a digital frequency divider function
whose incremental resolution is determined by the frequency of
the reference clock divided by the 2
N
number of bits in the
tuning word. The phase accumulator is a variable-modulus
counter that increments the number stored in it each time it
receives a clock pulse. When the counter overflows, it wraps
around, making the phase accumulator’s output contiguous.
The frequency tuning word sets the modulus of the counter,
which effectively determines the size of the increment (∆ Phase)
that is added to the value in the phase accumulator on the next
clock pulse. The larger the added increment, the faster the
accumulator overflows, which results in a higher output fre-
quency. The AD9850 uses an innovative and proprietary
algorithm that mathematically converts the 14-bit truncated
value of the phase accumulator to the appropriate COS value.
This unique algorithm uses a much reduced ROM look-up table
and DSP techniques to perform this function, which contributes
to the small size and low power dissipation of the AD9850. The
relationship of the output frequency, reference clock, and tuning
word of the AD9850 is determined by the formula
f
OUT
= (∆
Phase
×
CLKIN)/2
32
where:
∆
Phase
is the value of the 32-bit tuning word.
CLKIN
is the input reference clock frequency in MHz.
f
OUT
is the frequency of the output signal in MHz.
The digital sine wave output of the DDS block drives the inter-
nal high speed 10-bit D/A converter that reconstructs the sine
wave in analog form. This DAC has been optimized for dynamic
performance and low glitch energy as manifested in the low
jitter performance of the AD9850. Because the output of the
–8–
REV. H
AD [ ANALOG DEVICES ]
