AD9850
Table II. Factory Reserved Internal Test Control Codes
Loading Format
Factory Reserved Codes
Parallel
1) W0 = XXXXXX10
2) W0 = XXXXXX01
Serial
1) W32 = 1; W33 = 0
2) W32 = 0; W33 = 1
3) W32 = 1; W33 = 1
tCD
W0*
W1
W2
W3
W4
DATA
tDS
tWH
tDH
tWL
W CLK
tFD
tFL
tFH
FQ UD
CLKIN
tCF
VALID DATA
COS OUT
OLD FREQ (PHASE)
NEW FREQ (PHASE)
*OUTPUT UPDATE CAN OCCUR AFTER ANY WORD LOAD
AND IS ASYNCHRONOUS WITH THE REFERENCE CLOCK
SYMBOL DEFINITION
MINIMUM
3.5ns
tDS
tDH
tWH
tWL
tCD
tFH
tFL
DATA SETUP TIME
DATA HOLD TIME
3.5ns
W CLK HIGH
3.5ns
W CLK LOW
3.5ns
CLK DELAY AFTER FQ_UD
FQ UD HIGH
3.5ns
7.0ns
FQ UD LOW
7.0ns
tFD
tCF
FQ UD DELAY AFTER W CLK
OUTPUT LATENCY FROM FQ UD
7.0ns
FREQUENCY CHANGE 18 CLOCK CYCLES
PHASE CHANGE 13 CLOCK CYCLES
Figure 6. Parallel Load Frequency/Phase Update Timing Sequence
Table III. 8-Bit Parallel Load Data/Control Word Functional Assignment
Word
Data[7]
Phase-b4
(MSB)
Data[6]
Data[5]
Data[4]
Data[3]
Data[2]
Data[1]
Data[0]
W0
Phase-b3
Phase-b2
Phase-b1
Phase-b0
(LSB)
Power-Down
Control
Control
W1
Freq-b31
(MSB)
Freq-b30
Freq-b29
Freq-b28
Freq-b27
Freq-b26
Freq-b25
Freq-b24
W2
W3
W4
Freq-b23
Freq-b15
Freq-b7
Freq-b22
Freq-b14
Freq-b6
Freq-b21
Freq-b13
Freq-b5
Freq-b20
Freq-b12
Freq-b4
Freq-b19
Freq-b11
Freq-b3
Freq-b18
Freq-b10
Freq-b2
Freq-b17
Freq-b9
Freq-b1
Freq-b16
Freq-b8
Freq-b0
(LSB)
REV. H
–10–
ADI [ ADI ]
