AD9850
DATA (W0)
(PARALLEL)
XXXXX011
DATA (SERIAL)
REQUIRED TO RESET CONTROL REGISTERS
W32 = 0
W33 = 0
NOTE: W32 AND W33 SHOULD ALWAYS BE SET TO 0.
W CLK
FQ UD
LOAD 40-BIT SERIAL WORD
ENABLE SERIAL MODE
NOTE: FOR DEVICE START-UP IN SERIAL MODE, HARDWIRE PIN 2 AT 0, PIN 3 AT 1, AND PIN 4 AT 1
(SEE FIGURE 11).
Figure 10. Serial Load Enable Sequence
2
3
AD9850BRS
+V
SUPPLY
4
Figure 11. Pins 2 to 4 Connection for Default Serial Mode Operation
W0
W1
W2
W3
W39
DATA –
FQ UD
W CLK
40 W CLK CYCLES
Figure 12. Serial Load Frequency/Phase Update Sequence
Table IV. 40-Bit Serial Load Word Function Assignment
W0
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
Freq-b0 (LSB)
Freq-b1
Freq-b2
Freq-b3
Freq-b4
Freq-b5
Freq-b6
Freq-b7
Freq-b8
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
W26
W27
Freq-b14
Freq-b15
Freq-b16
Freq-b17
Freq-b18
Freq-b19
Freq-b20
Freq-b21
Freq-b22
Freq-b23
Freq-b24
Freq-b25
Freq-b26
Freq-b27
W28
W29
W30
W31
W32
W33
W34
W35
W36
W37
W38
W39
Freq-b28
Freq-b29
Freq-b30
Freq-b31 (MSB)
Control
Control
Power-Down
Phase-b0 (LSB)
Phase-b1
Phase-b2
Phase-b3
Freq-b9
Freq-b10
Freq-b11
Freq-b12
Freq-b13
Phase-b4 (MSB)
REV. H
–12–
ADI [ ADI ]
