AD9826
FUNCTIO NAL D ESCRIP TIO N
2-Channel CD S Mode
T he AD9826 can be operated in six different modes: 3-Channel
CDS Mode, 3-Channel SH A Mode, 2-Channel CDS Mode,
2-Channel SHA Mode, 1-Channel CDS Mode, and 1-Channel
SHA Mode. Each mode is selected by programming the Configura-
tion Registers through the serial interface. For more detail on
CDS or SHA mode operation, see the Circuit Operation section.
The 2-Channel Mode is selected by writing a “1” into two of the
channel select bits of the MUX register (D4–D6). Bit D5 of the
configuration register also needs to be set low to take the part out
of 3-Channel Mode. The channels that will be used is determined
by the contents of Bits D4–D6 of the MUX Configuration Reg-
ister (see T able III). T he combination of inputs that can be
selected are; RG, RB, or GB by writing a “1” into the appropri-
ate bit. T he sample order is selected by Bit D7. If D7 is high,
the MUX will sample in the following order: RG or RB or GB
depending on which channels are turned on. If Bit D7 is set low
the mux will sample in the following order: GR or BR or BG
depending on which channels are turned on.
3-Channel CD S Mode
In 3-Channel CDS Mode, the AD9826 simultaneously samples
the Red, Green, and Blue input voltages from the CCD outputs.
The sampling points for each Correlated Double Sampler (CDS)
are controlled by CDSCLK1 and CDSCLK2 (see Figures 11
and 13). CDSCLK1’s falling edge samples the reference level of
the CCD waveform. CDSCLK2’s falling edge samples the data
level of the CCD waveform. Each CDS amplifier outputs the
difference between the CCD’s reference and data levels. Next,
the output voltage of each CDS amplifier is level-shifted by an
Offset DAC. T he voltages are then scaled by the three Program-
mable Gain Amplifiers before being multiplexed through the
16-Bit ADC. T he ADC sequentially samples the PGA outputs
on the falling edges of ADCCLK.
T he AD9826 simultaneously samples the selected channels’
input voltages from the CCD outputs. T he sampling points
for each Correlated Double Sampler (CDS) are controlled by
CDSCLK1 and CDSCLK2 (see Figure 11). CDSCLK1’s fall-
ing edge samples the reference level of the CCD waveform.
CDSCLK2’s falling edge samples the data level of the CCD
waveform. Each CDS amplifier outputs the difference between
the CCD’s reference and data levels. Next, the output voltage of
each CDS amplifier is level-shifted by an Offset DAC. The volt-
ages are then scaled by the two Programmable Gain Amplifiers
before being multiplexed through the 16-bit ADC. T he ADC
sequentially samples the PGA outputs on the falling edges of
ADCCLK.
T he offset and gain values for the Red, Green, and Blue chan-
nels are programmed using the serial interface. T he order in
which the channels are switched through the multiplexer is
selected by programming the MUX Configuration register.
T iming for this mode is shown in Figure 1. It is recommended
that the falling edge of CDSCLK2 occur before the rising edge
of ADCCLK, although this is not required to satisfy the mini-
mum timing constraints. T he rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as
shown by tADC2. T he output data latency is three clock cycles.
T he offset and gain values for the Red, Green, and Blue chan-
nels are programmed using the serial interface. T he order in
which the channels are switched through the multiplexer is
selected by programming the MUX Configuration Register.
T iming for this mode is shown in Figure 3. T he rising edge of
CDSCLK2 should not occur before the previous falling edge of
ADCCLK, as shown by tADC2. T he output data latency is three
clock cycles.
3-Channel SH A Mode
In 3-Channel SHA Mode, the AD9826 simultaneously samples
the Red, Green, and Blue input voltages. T he sampling point is
controlled by CDSCLK2. CDSCLK2’s falling edge samples the
input waveforms on each channel. T he output voltages from the
three SHAs are modified by the offset DACs and then scaled by
the three PGAs. T he outputs of the PGAs are then multiplexed
through the 16-bit ADC. T he ADC sequentially samples the
PGA outputs on the falling edges of ADCCLK.
2-Channel SH A Mode
The 2-Channel Mode is selected by writing a “1” into two of the
channel select bits of the MUX Register (D4–D6). Bit D5 of the
configuration register also needs to be set low to take the part
out of 3-Channel Mode. T he channels that will be used is deter-
mined by the contents of Bits D4–D6 of the MUX Configuration
Register (see T able III ). T he combination of inputs that can be
selected are; RG, RB, or GB by writing a “1” into the appropri-
ate bit. T he sample order is selected by Bit D7. If D7 is high,
the mux will sample in the following order: RG or RB or GB,
depending on which channels are turned on. If Bit D7 is set low,
the mux will sample in the following order: GR or BR or BG,
depending on which channels are turned on.
T he input signal is sampled with respect to the voltage applied
to the OFFSET pin (see Figure 14). With the OFFSET pin
grounded, a zero volt input corresponds to the ADC’s zero scale
output. T he OFFSET pin may also be used as a coarse offset
adjust pin. A voltage applied to this pin will be subtracted from
the voltages applied to the Red, Green, and Blue inputs in the first
amplifier stage of the AD9826. The input clamp is disabled in this
mode. For more information, see the Circuit Operation section.
In 2-Channel SHA Mode, the AD9826 simultaneously samples
the selected channels’ input voltages. T he sampling point is
controlled by CDSCLK2. CDSCLK2’s falling edge samples the
input waveforms on each channel. T he output voltages from the
two SHAs are modified by the offset DACs and then scaled by
the two PGAs. T he outputs of the PGAs are then multiplexed
through the 16-bit ADC. The ADC sequentially samples the PGA
outputs on the falling edges of ADCCLK.
T iming for this mode is shown in Figure 5. CDSCLK1 should
be grounded in this mode. Although it is not required, it is recom-
mended that the falling edge of CDSCLK2 occur before the
rising edge of ADCCLK. T he rising edge of CDSCLK2 should
not occur before the previous falling edge of ADCCLK, as shown
by tADC2. T he output data latency is three ADCCLK cycles.
T he offset and gain values for the Red, Green, and Blue chan-
nels are programmed using the serial interface. T he order in
which the channels are switched through the multiplexer is
selected by programming the MUX Configuration register.
T he input signal is sampled with respect to the voltage applied
to the OFFSET pin (see Figure 14). With the OFFSET pin
grounded, a zero volt input corresponds to the ADC’s zero scale
output. T he OFFSET pin may also be used as a coarse offset
REV. A
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ADI [ ADI ]
