AD9772A
latched into the AD9772 on every other rising edge of the differ-
ential clock input. The rising edge that corresponds to the input
latch immediately precedes the rising edge of the 1ϫ clock at
PLLLOCK. Adequate setup and hold time for the input data as
shown in Figure 1b should be allowed. Note that enough delay
is present between CLK+/CLK– and the data input latch to
cause the minimum setup time for input data to be negative.
This is noted in the Digital Specifications section. PLLLOCK
contains a relatively weak driver output, with its output delay
(tOD) sensitive to output capacitance loading. Thus PLLLOCK
should be buffered for fanouts greater than one, and/or load
capacitance greater than 10 pF. If a data timing issue exists
between the AD9772A and its external driver device, the 1ϫ
clock appearing at PLLLOCK can be inverted via an external
gate to ensure proper setup and hold time.
DIGITAL DATA IN
DATA
EXTERNAL
tLPW
2ꢀ CLK
tPD
tPD
DELAYED INTERNAL
1ꢀ CLK
tD
LOAD DEPENDENT
DELAYED 1ꢀ CLK
AT PLLLOCK
I
OR I
OUTB
DATA ENTERS INPUT
LATCHES ON THIS EDGE
OUTA
Figure 12. Internal Timing of AD9772A with PLL Disabled
Figure 13 illustrates the details of the RESET function timing.
RESET going from a high to a low logic level enables the 1ϫ
clock output, generated by the PLLLOCK pin. If RESET goes
low at a time well before the rising edge of the 2ϫ clock, then
PLLLOCK will go high on the following edge of the 2ϫ clock. If
RESET goes from a high to a low logic level 600 ps or later
following the rising edge of the 2× clock, there will be a delay of
one 2ϫ clock cycle before PLLLOCK goes high. In either case,
as long as RESET remains low, PLLLOCK will change state on
every rising edge of the 2ϫ clock. As stated before, it is the rising
edge of the 2ϫ clock which immediately precedes the rising edge
of PLLLOCK that latches data into the AD9772A input latches.
CLK+ CLK–
CLKVDD PLLLOCK
+
–
AD9772A
PHASE
DETECTOR
CHARGE
PUMP
LPF
PLL
VDD
EXT/INT
CLOCK CONTROL
OUT1ꢀ
CLOCK
DISTRIBUTION
PLL
COM
PRESCALER
VCO
CLKCOM
MOD0 RESET
DIV1
DIV0
MOD1
Figure 11. Clock Multiplier with PLL Clock Multiplier
Disabled
.
SYNCHRONIZATION OF CLK/DATA USING RESET WITH
PLL DISABLED
CH1 2.00Vꢁ CH2 2.00Vꢁ M 10.0ns CH3 2.00Vꢁ
The relationship between the internal and external clocks in this
mode is shown in Figure 12. A clock at the output update data
rate (2ϫ the input data rate) must be applied to the CLK in-
puts. Internal dividers create the internal 1ϫ clock necessary for
the input latches. With the PLL disabled, a delayed version of the
1ϫ clock is present at the PLLLOCK pin. The DAC latch is
updated on the particular rising edge of the external 2ϫ clock
which corresponds to the rising edge of the 1ϫ clock. Updates
to the input data should be synchronized to this specific rising
edge as shown in Figure 12. To ensure this synchronization, a
Logic 1 should be momentarily applied to the RESET pin on
power up, before CLK is applied. Applying a momentary Logic 1
to RESET brings the 1ϫ clock at PLLLOCK to a Logic 1. On
the next rising edge of the 2ϫ clock, the 1ϫ clock will go to
Logic 0. The following rising edge of the 2ϫ clock will cause
the 1ϫ clock to Logic 1 again, as well as update the data in
both of the input latches.
[
]
T
a.
T
1
2
T
T
3
CH1 2.00Vꢁ CH2 2.00Vꢁ M 10.0ns CH4 1.20V
CH3 2.00Vꢁ
b.
Figure 13. RESET Timing of AD9772A with PLL Disabled
REV. A
–15–
ADI [ ADI ]
