AD9772A
can be synchronized in either mode if driven by the same
reference clock, since the PLL clock multiplier when enabled
ensures synchronization. RESET can be used for synchroniza-
tion if the PLL clock multiplier is disabled.
The effects of phase noise on the AD9772A’s SNR performance
becomes more noticeable at higher reconstructed output fre-
quencies and signal levels. Figure 9 compares the phase noise
of a full-scale sine wave at exactly fDATA/4 at different data rates
(hence carrier frequency) with the optimum DIV1, DIV0 setting.
The effects of phase noise, and its effect on a signal’s CNR
performance, becomes even more evident at higher IF fre-
quencies as shown in Figure 10. In both instances, it is the
“narrowband” phase noise that limits the CNR performance.
Figure 8 shows the proper configuration used to enable the PLL
clock multiplier. In this case, the external clock source is applied
to CLK+ (and/or CLK–) and the PLL clock multiplier is fully
enabled by connecting PLLVDD to CLKVDD.
The settling/acquisition time characteristics of the PLL are also
dependent on the divide-by-N ratio as well as the input data rate.
In general, the acquisition time increases with increasing data rate
(for fixed divide-by-N ratio) or increasing divide-by-N ratio (for
fixed input data rate).
0
–10
–20
–30
–40
Since the VCO can operate over a 96 MHz–400 MHz range,
the prescaler divide-by-ratio following the VCO must be set
–50
according to Table III for a given input data rate (i.e., fDATA
to ensure optimum phase noise and successful “locking.” In
general, the best phase noise performance for any prescaler
)
PLL ON, fDATA = 160MSPS
–60
PLL ON, fDATA = 100MSPS
–70
PLL ON, fDATA = 75MSPS
setting is achieved with the VCO operating near its maximum
output frequency of 400 MHz. Note, the divide-by-N ratio also
depends on whether the “zero stuffing” option is enabled since
this option requires the DAC to operate at four times the input
data rate. The divide-by-N ratio is set by DIV1 and DIV0.
–80
PLL ON, fDATA = 50MSPS
–90
–100
PLL OFF, fDATA = 50MSPS
–110
0
1
2
3
4
5
FREQUENCY OFFSET – MHz
With the PLL clock multiplier enabled, PLLLOCK serves as an
active HIGH control output which may be monitored upon sys-
tem power-up to indicate that the PLL is successfully “locked” to
the input clock. Note, when the PLL clock multiplier is NOT
locked, PLLLOCK will toggle between logic HIGH and LOW
in an asynchronous manner until locking is finally achieved.
As a result, it is recommended that PLLLOCK, if monitored,
be sampled several times to detect proper locking 100 ms
upon power-up.
Figure 9. Phase Noise of PLL Clock Multiplier at Exactly
fOUT = fDATA/4 at Different fDATA Settings with Optimum
DIV0/DIV1 Settings Using R & S FSEA30, RBW = 30 kHz
10
–10
–30
–50
Table III. Recommended Prescaler Divide-by-N Ratio Settings
fDATA
(MSPS)
Divide-by-N
Ratio
MOD1
DIV1
DIV0
–70
–90
48–160
24–100
12–50
6–25
24–100
12–50
6–25
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
–110
120
122
124
126
128
130
FREQUENCY – MHz
Figure 10. Direct IF Mode Reveals Phase Noise Degrada-
tion with and without PLL Clock Multiplier (IF = 125 MHz
and fDATA = 100 MSPS)
3–12.5
As stated earlier, applications requiring input data rates below
6 MSPS must disable the PLL clock multiplier and provide an
external reference clock. However, applications already contain-
ing a low phase noise (i.e., jitter) reference clock that is twice
(or four times) the input data rate should consider disabling the
PLL clock multiplier to achieve the best SNR performance from
the AD9772A. Note that the SFDR performance and wideband
noise performance of the AD9772A remains unaffected with or
without the PLL clock multiplier enabled.
To disable the PLL Clock Multiplier, connect PLLVDD to
PLLCOM as shown in Figure 11. LPF may remain open since
this portion of the PLL circuitry is now disabled. The differen-
tial clock input should be driven with a reference clock twice the
data input rate in baseband applications and four times the data
input rate in direct IF applications in which the “1/4 wave”
mixing option is employed (i.e., MOD1 and MOD0 active
HIGH). The clock distribution circuitry remains enabled pro-
viding a 1ϫ internal clock at PLLLOCK. Digital input data is
–14–
REV. A
ADI [ ADI ]
